HMAC Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.370s 890.931us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.900s 41.233us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.670s 13.892us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.860s 4.373ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.160s 575.775us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 8.705m 302.570ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.670s 13.892us 1 1 100.00
hmac_csr_aliasing 6.160s 575.775us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.640s 374.857us 1 1 100.00
V2 back_pressure hmac_back_pressure 1.020m 6.578ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.719m 24.383ms 1 1 100.00
hmac_test_sha384_vectors 6.710m 12.316ms 1 1 100.00
hmac_test_sha512_vectors 5.750m 55.907ms 1 1 100.00
hmac_test_hmac256_vectors 5.910s 385.803us 1 1 100.00
hmac_test_hmac384_vectors 6.820s 858.616us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 342.912us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.490s 5.621ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.203m 3.829ms 1 1 100.00
V2 error hmac_error 39.000s 2.160ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.198m 23.801ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.370s 890.931us 1 1 100.00
hmac_long_msg 15.640s 374.857us 1 1 100.00
hmac_back_pressure 1.020m 6.578ms 1 1 100.00
hmac_datapath_stress 8.203m 3.829ms 1 1 100.00
hmac_burst_wr 11.490s 5.621ms 1 1 100.00
hmac_stress_all 1.279m 17.810ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.370s 890.931us 1 1 100.00
hmac_long_msg 15.640s 374.857us 1 1 100.00
hmac_back_pressure 1.020m 6.578ms 1 1 100.00
hmac_datapath_stress 8.203m 3.829ms 1 1 100.00
hmac_wipe_secret 1.198m 23.801ms 1 1 100.00
hmac_test_sha256_vectors 2.719m 24.383ms 1 1 100.00
hmac_test_sha384_vectors 6.710m 12.316ms 1 1 100.00
hmac_test_sha512_vectors 5.750m 55.907ms 1 1 100.00
hmac_test_hmac256_vectors 5.910s 385.803us 1 1 100.00
hmac_test_hmac384_vectors 6.820s 858.616us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 342.912us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.370s 890.931us 1 1 100.00
hmac_long_msg 15.640s 374.857us 1 1 100.00
hmac_back_pressure 1.020m 6.578ms 1 1 100.00
hmac_datapath_stress 8.203m 3.829ms 1 1 100.00
hmac_burst_wr 11.490s 5.621ms 1 1 100.00
hmac_error 39.000s 2.160ms 1 1 100.00
hmac_wipe_secret 1.198m 23.801ms 1 1 100.00
hmac_test_sha256_vectors 2.719m 24.383ms 1 1 100.00
hmac_test_sha384_vectors 6.710m 12.316ms 1 1 100.00
hmac_test_sha512_vectors 5.750m 55.907ms 1 1 100.00
hmac_test_hmac256_vectors 5.910s 385.803us 1 1 100.00
hmac_test_hmac384_vectors 6.820s 858.616us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 342.912us 1 1 100.00
hmac_stress_all 1.279m 17.810ms 1 1 100.00
V2 stress_all hmac_stress_all 1.279m 17.810ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 47.098us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 12.660us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.820s 52.400us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.820s 52.400us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.900s 41.233us 1 1 100.00
hmac_csr_rw 0.670s 13.892us 1 1 100.00
hmac_csr_aliasing 6.160s 575.775us 1 1 100.00
hmac_same_csr_outstanding 1.390s 149.287us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.900s 41.233us 1 1 100.00
hmac_csr_rw 0.670s 13.892us 1 1 100.00
hmac_csr_aliasing 6.160s 575.775us 1 1 100.00
hmac_same_csr_outstanding 1.390s 149.287us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.930s 362.221us 1 1 100.00
hmac_tl_intg_err 2.890s 243.772us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.890s 243.772us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.370s 890.931us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.170s 242.739us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 3.587m 5.653ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.850s 38.726us 1 1 100.00
TOTAL 28 28 100.00