I2C Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.420s	1.529ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.670s	845.575us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.990s	51.963us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.920s	19.295us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.250s	1.985ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.600s	41.491us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.030s	39.626us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.920s	19.295us	1	1	100.00
		i2c_csr_aliasing	1.600s	41.491us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.030s	59.013us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	3.865m	92.942ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	43.440s	5.838ms	1	1	100.00
V2	host_override	i2c_host_override	0.750s	19.245us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.226m	15.612ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	36.140s	3.372ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.170s	422.439us	1	1	100.00
		i2c_host_fifo_fmt_empty	7.400s	537.214us	1	1	100.00
		i2c_host_fifo_reset_rx	10.100s	1.234ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	44.860s	4.015ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.090s	5.332ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.380s	143.370us	1	1	100.00
V2	target_glitch	i2c_target_glitch	2.130s	4.135ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	18.780s	60.992ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.300s	5.108ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	58.970s	9.939ms	1	1	100.00
		i2c_target_intr_smoke	3.570s	3.273ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.730s	1.145ms	1	1	100.00
		i2c_target_fifo_reset_tx	1.200s	635.770us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.310m	26.843ms	1	1	100.00
		i2c_target_stress_rd	58.970s	9.939ms	1	1	100.00
		i2c_target_intr_stress_wr	12.280s	8.458ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.730s	1.277ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	2.550s	385.065us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.480s	1.173ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.070s	10.226ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.310s	1.024ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.670s	267.585us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	43.440s	5.838ms	1	1	100.00
		i2c_host_perf_precise	10.100s	731.214us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.090s	5.332ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	7.730s	713.919us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.110s	494.766us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.870s	393.652us	1	1	100.00
		i2c_target_nack_txstretch	1.390s	258.677us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.110s	169.431us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.740s	2.311ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.620s	55.393us	1	1	100.00
V2	intr_test	i2c_intr_test	0.970s	16.070us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.610s	213.251us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.610s	213.251us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.990s	51.963us	1	1	100.00
		i2c_csr_rw	0.920s	19.295us	1	1	100.00
		i2c_csr_aliasing	1.600s	41.491us	1	1	100.00
		i2c_same_csr_outstanding	1.330s	81.577us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.990s	51.963us	1	1	100.00
		i2c_csr_rw	0.920s	19.295us	1	1	100.00
		i2c_csr_aliasing	1.600s	41.491us	1	1	100.00
		i2c_same_csr_outstanding	1.330s	81.577us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.300s	131.568us	1	1	100.00
		i2c_sec_cm	1.060s	67.655us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.300s	131.568us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	28.190s	2.755ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.250s	993.963us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.630s	3.541ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.43572161588089727338607676204741884491058499274597134354823756905297784342217
      Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2754790323 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2754790323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.3420507496578614920985370574384202811050507034135205651097055371133819592999
      Line 89, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3541473542 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3541473542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.51446390714325053216109649662721971375848033322943443245407193310836800349629
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  59013380 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  59013380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.11659648224086748241012499524160117759923556652279487583390617685263998269213
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 4135136545 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 4135136545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.11564003266814150265169957590494453962201361743413061518016393713955666087795
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 993962553 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 61 [0x3d])
        UVM_INFO @ 993962553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.114045980009095821442170060382842771898349015150426318686990134564125483925768
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10226443950 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10226443950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---