KEYMGR Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 3.210s 158.805us 1 1 100.00
V1 random keymgr_random 3.670s 206.476us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.980s 90.503us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.750s 57.619us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 4.930s 516.715us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.460s 489.573us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.050s 79.333us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.750s 57.619us 1 1 100.00
keymgr_csr_aliasing 5.460s 489.573us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 3.190s 114.066us 1 1 100.00
V2 sideload keymgr_sideload 2.510s 72.667us 1 1 100.00
keymgr_sideload_kmac 3.860s 193.478us 1 1 100.00
keymgr_sideload_aes 3.440s 171.335us 1 1 100.00
keymgr_sideload_otbn 1.990s 106.432us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 2.380s 162.148us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.080s 33.104us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.860s 218.593us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.440s 331.446us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.310s 148.075us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.540s 55.716us 1 1 100.00
V2 stress_all keymgr_stress_all 10.500s 1.512ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.660s 12.009us 1 1 100.00
V2 alert_test keymgr_alert_test 1.020s 34.659us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.440s 203.467us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.440s 203.467us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.980s 90.503us 1 1 100.00
keymgr_csr_rw 0.750s 57.619us 1 1 100.00
keymgr_csr_aliasing 5.460s 489.573us 1 1 100.00
keymgr_same_csr_outstanding 1.420s 214.514us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.980s 90.503us 1 1 100.00
keymgr_csr_rw 0.750s 57.619us 1 1 100.00
keymgr_csr_aliasing 5.460s 489.573us 1 1 100.00
keymgr_same_csr_outstanding 1.420s 214.514us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 7.560s 727.529us 1 1 100.00
keymgr_tl_intg_err 3.330s 267.622us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.900s 624.438us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.900s 624.438us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.900s 624.438us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.900s 624.438us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 3.380s 133.294us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.330s 267.622us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.900s 624.438us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 3.190s 114.066us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 3.670s 206.476us 1 1 100.00
keymgr_csr_rw 0.750s 57.619us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 3.670s 206.476us 1 1 100.00
keymgr_csr_rw 0.750s 57.619us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 3.670s 206.476us 1 1 100.00
keymgr_csr_rw 0.750s 57.619us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.080s 33.104us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.310s 148.075us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.310s 148.075us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 3.670s 206.476us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.500s 40.156us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 3.450s 126.037us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.080s 33.104us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 3.450s 126.037us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 3.450s 126.037us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 3.450s 126.037us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 7.560s 727.529us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 3.450s 126.037us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 6.210s 477.906us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00