49342f8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_dpe_smoke | 12.550s | 666.083us | 0 | 1 | 0.00 |
| V1 | csr_hw_reset | keymgr_dpe_csr_hw_reset | 0.810s | 40.734us | 1 | 1 | 100.00 |
| V1 | csr_rw | keymgr_dpe_csr_rw | 1.100s | 18.722us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | keymgr_dpe_csr_bit_bash | 3.190s | 180.165us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | keymgr_dpe_csr_aliasing | 6.400s | 267.144us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_dpe_csr_mem_rw_with_rand_reset | 1.910s | 51.191us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_dpe_csr_rw | 1.100s | 18.722us | 1 | 1 | 100.00 |
| keymgr_dpe_csr_aliasing | 6.400s | 267.144us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | intr_test | keymgr_dpe_intr_test | 0.670s | 18.296us | 1 | 1 | 100.00 |
| V2 | alert_test | keymgr_dpe_alert_test | 0.770s | 20.349us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_dpe_tl_errors | 1.300s | 447.285us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_dpe_tl_errors | 1.300s | 447.285us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_dpe_csr_hw_reset | 0.810s | 40.734us | 1 | 1 | 100.00 |
| keymgr_dpe_csr_rw | 1.100s | 18.722us | 1 | 1 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 6.400s | 267.144us | 1 | 1 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 2.080s | 72.545us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | keymgr_dpe_csr_hw_reset | 0.810s | 40.734us | 1 | 1 | 100.00 |
| keymgr_dpe_csr_rw | 1.100s | 18.722us | 1 | 1 | 100.00 | ||
| keymgr_dpe_csr_aliasing | 6.400s | 267.144us | 1 | 1 | 100.00 | ||
| keymgr_dpe_same_csr_outstanding | 2.080s | 72.545us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 4 | 4 | 100.00 | |||
| V2S | tl_intg_err | keymgr_dpe_sec_cm | 8.400s | 4.589ms | 1 | 1 | 100.00 |
| keymgr_dpe_tl_intg_err | 3.500s | 111.543us | 1 | 1 | 100.00 | ||
| V2S | shadow_reg_update_error | keymgr_dpe_shadow_reg_errors | 1.520s | 179.565us | 1 | 1 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_dpe_shadow_reg_errors | 1.520s | 179.565us | 1 | 1 | 100.00 |
| V2S | shadow_reg_storage_error | keymgr_dpe_shadow_reg_errors | 1.520s | 179.565us | 1 | 1 | 100.00 |
| V2S | shadowed_reset_glitch | keymgr_dpe_shadow_reg_errors | 1.520s | 179.565us | 1 | 1 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_dpe_shadow_reg_errors_with_csr_rw | 3.700s | 571.135us | 1 | 1 | 100.00 |
| V2S | prim_count_check | keymgr_dpe_sec_cm | 8.400s | 4.589ms | 1 | 1 | 100.00 |
| V2S | prim_fsm_check | keymgr_dpe_sec_cm | 8.400s | 4.589ms | 1 | 1 | 100.00 |
| V2S | TOTAL | 4 | 4 | 100.00 | |||
| TOTAL | 13 | 14 | 92.86 |
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
0.keymgr_dpe_smoke.8402384441828799396880288013937824989553004946255249584314736244447649538576
Line 4063, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_smoke/latest/run.log
UVM_ERROR @ 666083172 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 666083172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---