KMAC/UNMASKED Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	29.410s	7.746ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.990s	21.273us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.750s	22.797us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.750s	282.616us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.840s	3.878ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.910s	73.526us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.750s	22.797us	1	1	100.00
		kmac_csr_aliasing	3.840s	3.878ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.810s	23.025us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	0.980s	32.098us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	20.878m	250.340ms	1	1	100.00
V2	burst_write	kmac_burst_write	4.551m	8.694ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.195m	94.601ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.747m	306.044ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.010s	1.755ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.440s	279.431us	1	1	100.00
		kmac_test_vectors_shake_128	2.631m	39.782ms	1	1	100.00
		kmac_test_vectors_shake_256	1.209m	5.614ms	1	1	100.00
		kmac_test_vectors_kmac	1.980s	77.857us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.880s	58.135us	1	1	100.00
V2	sideload	kmac_sideload	2.482m	2.818ms	1	1	100.00
V2	app	kmac_app	1.391m	35.178ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.226m	2.715ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	13.660s	1.135ms	1	1	100.00
V2	error	kmac_error	3.789m	19.652ms	1	1	100.00
V2	key_error	kmac_key_error	1.880s	571.230us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.800s	497.029us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	25.580s	2.131ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.420s	458.519us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	17.230s	2.697ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.770s	125.936us	1	1	100.00
V2	stress_all	kmac_stress_all	5.842m	36.809ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.750s	17.241us	1	1	100.00
V2	alert_test	kmac_alert_test	1.100s	18.276us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.260s	83.022us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.260s	83.022us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.990s	21.273us	1	1	100.00
		kmac_csr_rw	0.750s	22.797us	1	1	100.00
		kmac_csr_aliasing	3.840s	3.878ms	1	1	100.00
		kmac_same_csr_outstanding	1.930s	100.497us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.990s	21.273us	1	1	100.00
		kmac_csr_rw	0.750s	22.797us	1	1	100.00
		kmac_csr_aliasing	3.840s	3.878ms	1	1	100.00
		kmac_same_csr_outstanding	1.930s	100.497us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.480s	131.025us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.480s	131.025us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.480s	131.025us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.480s	131.025us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.920s	280.944us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.040s	8.595ms	1	1	100.00
		kmac_tl_intg_err	2.040s	97.826us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.040s	97.826us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.770s	125.936us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	29.410s	7.746ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.482m	2.818ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.480s	131.025us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.040s	8.595ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.040s	8.595ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.040s	8.595ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	29.410s	7.746ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.770s	125.936us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.040s	8.595ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	11.900s	440.808us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	29.410s	7.746ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	34.670s	3.358ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.99464455742583400345128301080523576183371036298812913653939576202683062103947
      Line 102, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3357532172 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3357532172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---