ROM_CTRL/32KB Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.070s	176.849us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.280s	549.510us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.420s	292.306us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.260s	205.833us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.290s	557.189us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.030s	308.314us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.420s	292.306us	1	1	100.00
		rom_ctrl_csr_aliasing	5.290s	557.189us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	3.720s	1.584ms	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.480s	175.696us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	4.190s	138.744us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	16.290s	2.171ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.860s	403.477us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.970s	1.340ms	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.860s	166.942us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.860s	166.942us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.280s	549.510us	1	1	100.00
		rom_ctrl_csr_rw	5.420s	292.306us	1	1	100.00
		rom_ctrl_csr_aliasing	5.290s	557.189us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.570s	185.503us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.280s	549.510us	1	1	100.00
		rom_ctrl_csr_rw	5.420s	292.306us	1	1	100.00
		rom_ctrl_csr_aliasing	5.290s	557.189us	1	1	100.00
		rom_ctrl_same_csr_outstanding	4.570s	185.503us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	11.650s	773.016us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
		rom_ctrl_tl_intg_err	43.260s	1.067ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.070s	176.849us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.070s	176.849us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.070s	176.849us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	43.260s	1.067ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
		rom_ctrl_kmac_err_chk	8.860s	403.477us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	35.460s	625.394us	0	1	0.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	11.650s	773.016us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	1.677m	781.469us	0	1	0.00
V2S		TOTAL			2	4	50.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	51.940s	7.187ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.10139056418666244794745962656394716852868899127887010328179486706576103430888
      Line 104, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 625394326 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 625394326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.51761624891853779939564827355503691636986083893704832936684393340518584295607
      Line 243, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 37740974ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 37740974ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 37740974ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))