49342f8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.880s | 49.711us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.670s | 25.625us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.630s | 18.775us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.540s | 143.291us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.660s | 29.207us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.960s | 108.241us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.630s | 18.775us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.660s | 29.207us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.930s | 446.700us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.990s | 2.643ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 4.575m | 771.622ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 4.575m | 771.622ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 4.890s | 3.956ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.550s | 19.625us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.710s | 43.348us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.900s | 180.072us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.900s | 180.072us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.670s | 25.625us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.630s | 18.775us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.660s | 29.207us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.940s | 18.928us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.670s | 25.625us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.630s | 18.775us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.660s | 29.207us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.940s | 18.928us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.870s | 300.222us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.770s | 837.054us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.770s | 837.054us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.030s | 1.583ms | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.670s | 44.374us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 1.230s | 109.385us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 15 | 19 | 78.95 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.23524697316863433688891677770959387331334429123914196939995819429846003627473
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 1583386147 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5b3b8504) == 0x1
UVM_INFO @ 1583386147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.61057883040789973170521443957404870532428314430344584356376419439297694307423
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 446699768 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x51a0bf04) == 0x1
UVM_INFO @ 446699768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.71361124856302583558188943319064784380241899011619462449091771754283729878549
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 44374417 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44374417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
0.rv_timer_stress_all_with_rand_reset.92948950873804501890874587215881736599589534725394328365586213691783536503510
Line 97, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 109384655 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 109384655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---