SPI_DEVICE/1R1W Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	34.150s	4.215ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.030s	47.784us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.640s	56.211us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.240s	7.851ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.390s	776.702us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.620s	109.207us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.640s	56.211us	1	1	100.00
		spi_device_csr_aliasing	11.390s	776.702us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.920s	24.882us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.960s	278.341us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.960s	30.487us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.880s	2.301us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.960s	6.617us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.190s	178.307us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.190s	178.307us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	7.420s	30.738ms	1	1	100.00
		spi_device_tpm_sts_read	0.880s	17.441us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	8.980s	1.145ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	7.910s	25.043ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.030s	116.984us	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.030s	116.984us	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	6.700s	2.141ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	6.700s	2.141ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	6.700s	2.141ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	6.700s	2.141ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	6.700s	2.141ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.590s	744.269us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	22.650s	2.759ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	22.650s	2.759ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	22.650s	2.759ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.420s	433.405us	1	1	100.00
		spi_device_read_buffer_direct	8.380s	1.400ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	22.650s	2.759ms	1	1	100.00
		spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	56.420s	12.220ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.460s	135.011us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.460s	135.011us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	34.150s	4.215ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.013m	16.773ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.920s	199.409us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.770s	36.541us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.010s	13.231us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.110s	228.559us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.110s	228.559us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.030s	47.784us	1	1	100.00
		spi_device_csr_rw	1.640s	56.211us	1	1	100.00
		spi_device_csr_aliasing	11.390s	776.702us	1	1	100.00
		spi_device_same_csr_outstanding	2.330s	146.035us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.030s	47.784us	1	1	100.00
		spi_device_csr_rw	1.640s	56.211us	1	1	100.00
		spi_device_csr_aliasing	11.390s	776.702us	1	1	100.00
		spi_device_same_csr_outstanding	2.330s	146.035us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.210s	67.594us	1	1	100.00
		spi_device_tl_intg_err	17.410s	2.665ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.410s	2.665ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.110s	13.838us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.69569551713473698364171792721893730324804815689443837194286009054785462403936
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1954756 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[109])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1954756 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1954756 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.38515693950558620116034705944845770902660143404948482764316618706436846601524
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4325195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x59d1d6 [10110011101000111010110] vs 0x0 [0])
        UVM_ERROR @   4330195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17b5ba [101111011010110111010] vs 0x0 [0])
        UVM_ERROR @   4346195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf09a0f [111100001001101000001111] vs 0x0 [0])
        UVM_ERROR @   4383195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x67c6c7 [11001111100011011000111] vs 0x0 [0])
        UVM_ERROR @   4385195 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9ba82a [100110111010100000101010] vs 0x0 [0])