SPI_HOST Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	1.790ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	16.871us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	15.685us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	238.682us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	313.260us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	75.484us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	15.685us	1	1	100.00
		spi_host_csr_aliasing	1.000s	313.260us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	107.400us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	60.799us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	123.246us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	74.910us	1	1	100.00
		spi_host_error_cmd	2.000s	18.877us	1	1	100.00
		spi_host_event	17.000s	599.709us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	145.108us	1	1	100.00
V2	speed	spi_host_speed	3.000s	145.108us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	145.108us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	2.000s	74.061us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	39.352us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	145.108us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	145.108us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	1.790ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	1.790ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	198.746us	1	1	100.00
V2	spien	spi_host_spien	6.000s	723.309us	1	1	100.00
V2	stall	spi_host_status_stall	2.283m	44.821ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	84.990us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	74.910us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	49.625us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	38.635us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	38.547us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	38.547us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	16.871us	1	1	100.00
		spi_host_csr_rw	2.000s	15.685us	1	1	100.00
		spi_host_csr_aliasing	1.000s	313.260us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	59.294us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	16.871us	1	1	100.00
		spi_host_csr_rw	2.000s	15.685us	1	1	100.00
		spi_host_csr_aliasing	1.000s	313.260us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	59.294us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	355.981us	1	1	100.00
		spi_host_sec_cm	1.000s	292.626us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	355.981us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.117m	9.833ms	1	1	100.00
		TOTAL			26	26	100.00