SRAM_CTRL/MAIN Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	32.770s	1.161ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.820s	37.689us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.910s	35.828us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.290s	339.401us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.980s	68.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.420s	366.436us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.910s	35.828us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	68.094us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.362m	138.050ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.156m	62.354ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.191m	8.573ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.135m	18.316ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.496m	143.741ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	13.965m	94.945ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.070s	13.567ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.140m	17.093ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.880s	3.611ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.574m	78.616ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.290s	2.880ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	11.370s	7.062ms	1	1	100.00
		sram_ctrl_throughput_w_readback	42.940s	17.578ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.543m	10.439ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.130s	344.188us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	26.434m	20.885ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.670s	23.529us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.550s	132.733us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.550s	132.733us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.820s	37.689us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	35.828us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	68.094us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	15.951us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.820s	37.689us	1	1	100.00
		sram_ctrl_csr_rw	0.910s	35.828us	1	1	100.00
		sram_ctrl_csr_aliasing	0.980s	68.094us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	15.951us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.330s	3.740ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
		sram_ctrl_tl_intg_err	1.750s	87.495us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.750s	87.495us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.543m	10.439ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.543m	10.439ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.910s	35.828us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.140m	17.093ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.140m	17.093ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.140m	17.093ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.070s	13.567ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.980s	760.386us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.330s	3.740ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.060s	675.423us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	32.770s	1.161ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	32.770s	1.161ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.140m	17.093ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.070s	13.567ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	32.770s	1.161ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.070s	6.850us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.330s	5.214ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.84472654515520561477858445200103882819132896467405876332316874389156213674563
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 675423054 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5a) != exp (0x68)
        UVM_INFO @ 675423054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.52135721523011404164569440048561314942329499744501545347080264585349473512776
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6849810 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6849810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---