SRAM_CTRL/RET Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.960s	377.545us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.970s	17.533us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.880s	14.951us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.520s	475.521us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.850s	141.130us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.070s	125.316us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.880s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.850s	141.130us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.090s	451.021us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.450s	527.829us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	13.217m	42.561ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.667m	2.213ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	52.440s	3.436ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	50.190s	506.003us	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.310s	2.823ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.277m	20.757ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	39.920s	2.038ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.460m	22.527ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.310s	1.849ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	3.440s	57.995us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.420s	49.579us	1	1	100.00
V2	regwen	sram_ctrl_regwen	44.570s	1.509ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.920s	128.840us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	24.623m	44.140ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.870s	20.544us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.180s	424.838us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.180s	424.838us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.970s	17.533us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.850s	141.130us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.120s	23.372us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.970s	17.533us	1	1	100.00
		sram_ctrl_csr_rw	0.880s	14.951us	1	1	100.00
		sram_ctrl_csr_aliasing	0.850s	141.130us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.120s	23.372us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.520s	394.301us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
		sram_ctrl_tl_intg_err	1.890s	186.060us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.890s	186.060us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	44.570s	1.509ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	44.570s	1.509ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.880s	14.951us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.277m	20.757ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.277m	20.757ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.277m	20.757ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.310s	2.823ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.930s	41.464us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.520s	394.301us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.890s	59.994us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.960s	377.545us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.960s	377.545us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.277m	20.757ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.310s	2.823ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.960s	377.545us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	3.451us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	28.110s	2.531ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36656578006706196565579081071342989565628056433546752172951651501367544289582
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3451339 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3451339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---