UART Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: 49342f8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.850s	510.591us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.800s	18.332us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.630s	24.713us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.290s	33.626us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.950s	58.922us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.830s	100.426us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.630s	24.713us	1	1	100.00
		uart_csr_aliasing	0.950s	58.922us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	13.790s	27.685ms	1	1	100.00
V2	parity	uart_smoke	2.850s	510.591us	1	1	100.00
		uart_tx_rx	13.790s	27.685ms	1	1	100.00
V2	parity_error	uart_intr	23.480s	110.894ms	1	1	100.00
		uart_rx_parity_err	43.660s	32.558ms	1	1	100.00
V2	watermark	uart_tx_rx	13.790s	27.685ms	1	1	100.00
		uart_intr	23.480s	110.894ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.428m	72.858ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	18.540s	26.176ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	16.690s	76.568ms	1	1	100.00
V2	rx_frame_err	uart_intr	23.480s	110.894ms	1	1	100.00
V2	rx_break_err	uart_intr	23.480s	110.894ms	1	1	100.00
V2	rx_timeout	uart_intr	23.480s	110.894ms	1	1	100.00
V2	perf	uart_perf	55.580s	30.533ms	1	1	100.00
V2	sys_loopback	uart_loopback	14.070s	8.689ms	1	1	100.00
V2	line_loopback	uart_loopback	14.070s	8.689ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.220s	46.165ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	9.250s	61.243ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.220s	1.472ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.830s	5.730ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	7.896m	211.718ms	1	1	100.00
V2	stress_all	uart_stress_all	2.871m	112.175ms	1	1	100.00
V2	alert_test	uart_alert_test	0.740s	30.589us	1	1	100.00
V2	intr_test	uart_intr_test	0.690s	82.153us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.500s	754.420us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.500s	754.420us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.800s	18.332us	1	1	100.00
		uart_csr_rw	0.630s	24.713us	1	1	100.00
		uart_csr_aliasing	0.950s	58.922us	1	1	100.00
		uart_same_csr_outstanding	0.940s	50.498us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.800s	18.332us	1	1	100.00
		uart_csr_rw	0.630s	24.713us	1	1	100.00
		uart_csr_aliasing	0.950s	58.922us	1	1	100.00
		uart_same_csr_outstanding	0.940s	50.498us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.140s	73.496us	1	1	100.00
		uart_tl_intg_err	1.170s	49.761us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.170s	49.761us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.580s	9.086ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.98183160062825725466672074311740152802976636114947652430695628706009648285877
      Line 76, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 36618934140 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 36618992964 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 36619169436 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (43 [0x2b] vs 254 [0xfe]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 37055819988 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 37055878812 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty