CHIP Simulation Results

Monday October 13 2025 16:01:27 UTC

GitHub Revision: `49342f8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.955m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.955m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.192m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	58.842s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	43.796s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.601m	5.629ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.601m	5.629ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.601m	5.629ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	37.170s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	2.349m		0	1	0.00
		chip_sw_example_concurrency	4.173m	3.045ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.446s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.870s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	8.420s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	8.420s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.160s	11.239us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.786m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.865m	10.076ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.960m	5.938ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.911s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.920s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	15.117s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	14.885s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.800s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.800s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.924m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.846m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.974m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.974m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.464m	4.244ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.964m	3.717ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.079m	14.645ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.801s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.519s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	20.565m	26.353ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.554m	5.595ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.005m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.005m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.523s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.965m	4.811ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.965m	4.811ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.428m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.889m	5.556ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.519m	4.508ms	1	1	100.00
		chip_sw_aes_idle	4.703m	5.620ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.640m	5.388ms	1	1	100.00
		chip_sw_kmac_idle	3.527m	4.193ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.844m	11.477ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	14.541m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.944m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.647m	11.736ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.009s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.412s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.520s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.407s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.867s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.603s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.009s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.412s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.520s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.407s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.867s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.603s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.635s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.480s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.940s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.800s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.150s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	17.964s		0	1	0.00
		chip_sw_clkmgr_jitter	4.834m	5.119ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.480m	3.475ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.726s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	37.090s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	36.380s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	37.650s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.330s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	38.650s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.154s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.704s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.478s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	16.649s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.360m	17.431ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.965m	4.811ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.647s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.360m	17.431ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	18.463s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.143s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.623s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.393s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.885s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.079m	14.645ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.221m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.834m	8.080ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.608m	6.647ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.756m	4.667ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.723s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.500s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.313s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.608m	6.647ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.062s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.447s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.696s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.301s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.636s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.269s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.500s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.356s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.531m	6.370ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.210s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.682s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.736s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	22.624s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.514m	6.463ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	11.659m	13.426ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	17.256s		0	1	0.00
		chip_prim_tl_access	17.634m	26.507ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.009s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	15.412s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.520s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.407s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.867s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.812s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.603s		0	1	0.00
		chip_rv_dm_lc_disabled	20.565m	26.353ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.314m	5.042ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	40.480s	10.180us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.433m	4.760ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.703m	5.620ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.286m	4.684ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	38.940s	10.100us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.640m	5.388ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.177m	4.729ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.882m	3.504ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	39.150s	10.340us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.514m	6.463ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	33.400s	10.340us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.155m	5.888ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.527m	4.193ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.476s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.476s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.582s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.714m	4.055ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.755s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.514m	6.463ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.800s	10.140us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.348s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.635s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.519m	4.508ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.519m	4.508ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.519m	4.508ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.173m	7.174ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.659m	13.426ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.659m	13.426ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.034m	7.476ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	17.964s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.256s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.974m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.173m	7.174ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.514m	6.463ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.034m	7.476ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.437m	4.836ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.173m	7.174ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.514m	6.463ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.034m	7.476ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.437m	4.836ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.030s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.356s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.210s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	19.682s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	12.736s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	22.624s		0	1	0.00
		chip_sw_lc_ctrl_transition	19.085s		0	1	0.00
		chip_prim_tl_access	17.634m	26.507ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	17.634m	26.507ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	14.958s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.097s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.704s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.635s		0	1	0.00
		chip_sw_aes_enc_jitter_en	40.480s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.940s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.800s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.150s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	17.964s		0	1	0.00
		chip_sw_clkmgr_jitter	4.834m	5.119ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.242m	10.330ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.242m	10.330ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.615m	5.658ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.122m	3.971ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.030m	4.254ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.364m	5.763ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.061m	5.510ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.356m	3.504ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.437m	4.836ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.221m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.221m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.585m	4.298ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.748m	5.615ms	1	1	100.00
		chip_sw_clkmgr_smoketest	4.155m	5.772ms	1	1	100.00
		chip_sw_csrng_smoketest	3.579m	5.585ms	1	1	100.00
		chip_sw_gpio_smoketest	4.097m	5.915ms	1	1	100.00
		chip_sw_hmac_smoketest	4.522m	4.051ms	1	1	100.00
		chip_sw_kmac_smoketest	4.223m	4.407ms	1	1	100.00
		chip_sw_otbn_smoketest	5.635m	6.133ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.097m	5.100ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.534m	3.713ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.673m	6.946ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.190m	5.323ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.322m	4.391ms	1	1	100.00
		chip_sw_uart_smoketest	3.931m	4.488ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.241s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.446s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.786m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.733s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.446m	4.926ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.605m	5.813ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.491m	5.510ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.559m	6.080ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.487s		0	1	0.00
		chip_rv_dm_lc_disabled	20.565m	26.353ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	15.712s		0	1	0.00
		chip_sw_lc_walkthrough_prod	18.090s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	14.050s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.989s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.487s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	12.617s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.661s		0	1	0.00
		rom_volatile_raw_unlock	11.683s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.275s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.294m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.652m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.781m	5.656ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.781m	5.656ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	8.420s		0	1	0.00
		chip_same_csr_outstanding	8.440s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	8.420s		0	1	0.00
		chip_same_csr_outstanding	8.440s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.409m	73.785us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	10.250s	11.417us	1	1	100.00
		xbar_smoke_large_delays	5.100m	2.630ms	1	1	100.00
		xbar_smoke_slow_rsp	5.482m	1.996ms	1	1	100.00
		xbar_random_zero_delays	7.910s	8.760us	1	1	100.00
		xbar_random_large_delays	18.601m	9.297ms	1	1	100.00
		xbar_random_slow_rsp	4.016m	1.466ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	54.330s	31.889us	1	1	100.00
		xbar_error_and_unmapped_addr	24.790s	19.709us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.322m	225.636us	1	1	100.00
		xbar_error_and_unmapped_addr	24.790s	19.709us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	23.810s	47.674us	1	1	100.00
		xbar_access_same_device_slow_rsp	53.581m	20.814ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.253m	68.517us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.794m	94.059us	1	1	100.00
		xbar_stress_all_with_error	4.457m	253.895us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	34.139m	3.068ms	1	1	100.00
		xbar_stress_all_with_reset_error	8.921m	577.153us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.990s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	14.201s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.572s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.069s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.798s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.733s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.576s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.837s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.505s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.478s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.327s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.473s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.076s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	43.300s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	50.704s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	44.409s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	36.838s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	41.004s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	31.858s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	38.369s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	31.340s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	28.444s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	32.243s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	34.580s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	27.943s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	29.572s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.268s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.460s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.818s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.154s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.784s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.267s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.590s		0	1	0.00
		rom_e2e_asm_init_dev	12.709s		0	1	0.00
		rom_e2e_asm_init_prod	12.304s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.314s		0	1	0.00
		rom_e2e_asm_init_rma	12.674s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.288s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.462s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.414s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.547s		0	1	0.00
V2		TOTAL			67	205	32.68
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.315m	4.887ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.472m	4.155ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.269s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.225s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.769s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.619s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.107m	16.824ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	17.366s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	20.015m	16.420ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.711s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.010s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.269s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.225s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.769s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.654s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.623s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.674s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.755s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	22.961m	12.944ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.299m	3.697ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.640m	4.625ms	1	1	100.00
		chip_plic_all_irqs_0	9.773m	5.127ms	1	1	100.00
		chip_plic_all_irqs_10	11.003m	5.763ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.672m	5.190ms	1	1	100.00
		chip_sw_dma_abort	4.022m	4.003ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.519s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.127s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.515s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.517s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.234s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.498s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.419s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.814s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.240s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.375s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.428m	4.218ms	1	1	100.00
		chip_sw_mbx_smoketest	4.958m	5.667ms	1	1	100.00
		TOTAL			81	250	32.40

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.106257835495026747050749160914829596472380382586681213967653303432695591598182
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.238s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.43285103088677570300491855045328727491428765615110502370281807826961781336120
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.334s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.105328726214898203140341350757981570662507133739339369816098614205772523733049
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.232s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.100307518418835648400983956682621875375504436520518734567235520184783613109672
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 99.800s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.51480055445064612874198753692930932120792786259098383080006869458653523379724
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 106.631s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.55598554824581947248310600743113963346317758110327476530301226204304093901206
    Line 386, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.94263197517180617452999281346477486979808323085151080596762239606058749683713
    Line 382, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.66236009505702915411928660263391373602242353630909632611264510892002486811693
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.68835848815424557125185012617595152582209501854422872853209090486917438968835
    Line 383, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.49858682787177255071526370654369997453248073824830250157339211610498537025666
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.72771620144138635614782021861091466956522595799023001416400803287844625536436
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.16979465613527572233724507517637112152339814344017797497574676333950038780865
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.56700736096471326932184304672468637551087994903460193049823996223825852876081
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.45500597587886204175984870388822723232425965418189377451978362055113881819447
Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.404479 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.404479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.86394502913519550524098658444367082777576811753828654927845889858389461672789
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.789100 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.789100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.50348654185162619729913269482919494454662524081906798426936123258366290806135
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.576480 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.576480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.40600195704810143782547914100700383489803229604746340945366580149058376075666
Line 410, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6463.344508 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (382623753112746197867022494500952821802248692700733308805538646919805946302192151665069973894702918209206008645806123829820983369804343194098377083411548 [0x74e39d7aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3811889267f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6463.344508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.105323251159191622920522497999471041030559130360160459046585675539986180237593
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6369.949136 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1441081731254854912756456288327674287594276138889159127015115631733535458318113349716890364311583938475021284784414060215994736643885121570089923422542940 [0x1b83dc5baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd39dd56caa7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6369.949136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 2 failures:
- Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_hmac_trans.64345956408507269903083745299342791060285753839241293848926737189103359637823
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.624455 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.624455 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
  - 0.chip_sw_clkmgr_off_kmac_trans.67298669969208267407997256007612435275268860742523539046799015114642401748487
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
```
  UVM_ERROR @ 12018.490010 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.490010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.13728571128920377030751638824018431729510465982077141869981827831646970511492
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4243.539300 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h8209223e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h0  a_user: 'h26956  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4243.539300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.41823336247447373148605309456027004384834909298179310335112886255301252907781
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3717.145209 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h8f5f8b24  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h35  a_opcode: 'h1  a_user: 'h248a7  d_param: 'h0  d_source: 'h35  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3717.145209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.72464338636588174635167011157355668058555389126073717881139200583332370283805
    Line 1346, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.30181327055065500168728460111901491729048439316167218195412030475560079730349
    Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5938.016724 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5938.016724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.56472550196907320452056053806660255736728578022479100177055634288606371927087
    Line 638, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6647.470410 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6647.470410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.96047061898206013432161387536359783868733778895081603552357538737834968760945
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5658.045145 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5658.045145 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.94078692086890473021824909871242109136328884133639639729207153616013242651395
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 3970.774652 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 3970.774652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.9206831277089664250063037174578192685907589180506383864512388582823679504702
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4811.242680 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4811.242680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.59663086376508510103731752916692875857370766673622514494081958310486775351846
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5763.286268 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5763.286268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.84267902884363520122562994701804379762193656008869049258867738490047529863325
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36518) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.81047272271848435273156073034096914013276945677783961808642674012747810033047
Line 231, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5655.654108 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36518) { a_addr: 'h406fc  a_data: 'h409b63f3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h185f9  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5655.654108 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.63819935666758288297676235822720805787525300415399743124245200245473248025112
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14644.645132 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14644.645132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.77459922375579816280991488871303683957078687399925604879387558023624729961999
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.18226951221623186167778495269256683149766262259484671359250349604489497970577
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4003.498592 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4003.498592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```