CSRNG Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	3.000s	41.300us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	62.881us	1	1	100.00
V1	csr_rw	csrng_csr_rw	2.000s	26.606us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	2.925ms	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	4.000s	91.842us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.000s	36.756us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.000s	26.606us	1	1	100.00
		csrng_csr_aliasing	4.000s	91.842us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	6.000s	195.903us	1	1	100.00
V2	alerts	csrng_alert	12.000s	703.500us	1	1	100.00
V2	err	csrng_err	2.000s	40.935us	1	1	100.00
V2	cmds	csrng_cmds	2.283m	12.312ms	1	1	100.00
V2	life cycle	csrng_cmds	2.283m	12.312ms	1	1	100.00
V2	stress_all	csrng_stress_all	55.000s	1.490ms	0	1	0.00
V2	intr_test	csrng_intr_test	2.000s	30.730us	1	1	100.00
V2	alert_test	csrng_alert_test	2.000s	62.921us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	1.153ms	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	1.153ms	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	62.881us	1	1	100.00
		csrng_csr_rw	2.000s	26.606us	1	1	100.00
		csrng_csr_aliasing	4.000s	91.842us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	128.420us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	62.881us	1	1	100.00
		csrng_csr_rw	2.000s	26.606us	1	1	100.00
		csrng_csr_aliasing	4.000s	91.842us	1	1	100.00
		csrng_same_csr_outstanding	3.000s	128.420us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	3.000s	149.976us	1	1	100.00
		csrng_tl_intg_err	9.000s	787.194us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	2.000s	46.815us	1	1	100.00
		csrng_csr_rw	2.000s	26.606us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	12.000s	703.500us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	55.000s	1.490ms	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	12.000s	703.500us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	55.000s	1.490ms	0	1	0.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	12.000s	703.500us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	787.194us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
		csrng_sec_cm	3.000s	149.976us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	6.000s	195.903us	1	1	100.00
		csrng_err	2.000s	40.935us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.683m	4.115ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
  • Test csrng_stress_all has 1 failures.

    • 0.csrng_stress_all.91440867841543734685848884992510365652307021937902787969362873194395939705071
      Line 148, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

        UVM_ERROR @ 1489804790 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 1489804790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---