DMA Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	313.318us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	3.397ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	1.115ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	281.120us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	71.589us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	588.803us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	246.033us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	101.867us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	71.589us	1	1	100.00
		dma_csr_aliasing	3.000s	246.033us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	45.000s	3.760ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	12.767m	68.046ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.800m	40.615ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.800m	40.615ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	12.767m	68.046ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.783m	31.417ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.800m	40.615ms	1	1	100.00
V2	dma_abort	dma_abort	13.000s	1.227ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.183m	22.248ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	14.467us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	29.795us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	209.821us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	209.821us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	281.120us	1	1	100.00
		dma_csr_rw	1.000s	71.589us	1	1	100.00
		dma_csr_aliasing	3.000s	246.033us	1	1	100.00
		dma_same_csr_outstanding	3.000s	79.566us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	281.120us	1	1	100.00
		dma_csr_rw	1.000s	71.589us	1	1	100.00
		dma_csr_aliasing	3.000s	246.033us	1	1	100.00
		dma_same_csr_outstanding	3.000s	79.566us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	95.029us	1	1	100.00
		dma_generic_stress	2.783m	31.417ms	1	1	100.00
		dma_handshake_stress	1.800m	40.615ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	7.000s	596.522us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	196.083us	1	1	100.00
		dma_sec_cm	1.000s	10.533us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.017m	11.867ms	1	1	100.00
		dma_longer_transfer	16.000s	2.653ms	1	1	100.00
		dma_stress_all_with_rand_reset	13.000s	977.668us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.18584162308387288428049661365680024593749255294153703399927036430193088261230
      Line 110, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  977668396ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  977668396ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---