EDN Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.880s	28.141us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.780s	40.719us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.810s	54.817us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.570s	495.241us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.060s	16.890us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.220s	113.960us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.810s	54.817us	1	1	100.00
		edn_csr_aliasing	1.060s	16.890us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.050s	61.048us	1	1	100.00
V2	csrng_commands	edn_genbits	1.050s	61.048us	1	1	100.00
V2	genbits	edn_genbits	1.050s	61.048us	1	1	100.00
V2	interrupts	edn_intr	1.010s	26.879us	1	1	100.00
V2	alerts	edn_alert	0.930s	328.176us	1	1	100.00
V2	errs	edn_err	0.990s	183.468us	1	1	100.00
V2	disable	edn_disable	0.800s	14.331us	1	1	100.00
		edn_disable_auto_req_mode	1.010s	33.563us	1	1	100.00
V2	stress_all	edn_stress_all	3.870s	285.780us	1	1	100.00
V2	intr_test	edn_intr_test	0.740s	12.525us	1	1	100.00
V2	alert_test	edn_alert_test	0.810s	215.697us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.410s	303.915us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.410s	303.915us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.780s	40.719us	1	1	100.00
		edn_csr_rw	0.810s	54.817us	1	1	100.00
		edn_csr_aliasing	1.060s	16.890us	1	1	100.00
		edn_same_csr_outstanding	0.850s	25.051us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.780s	40.719us	1	1	100.00
		edn_csr_rw	0.810s	54.817us	1	1	100.00
		edn_csr_aliasing	1.060s	16.890us	1	1	100.00
		edn_same_csr_outstanding	0.850s	25.051us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.130s	348.575us	1	1	100.00
		edn_tl_intg_err	1.540s	101.255us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.910s	19.150us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.930s	328.176us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.130s	348.575us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.130s	348.575us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.130s	348.575us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.130s	348.575us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.930s	328.176us	1	1	100.00
		edn_sec_cm	3.130s	348.575us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.930s	328.176us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.540s	101.255us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.363m	4.647ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00