HMAC Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.630s 3.770ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.890s 201.799us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.770s 18.232us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.720s 112.120us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.210s 162.484us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.690s 247.358us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.770s 18.232us 1 1 100.00
hmac_csr_aliasing 5.210s 162.484us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 44.230s 1.170ms 1 1 100.00
V2 back_pressure hmac_back_pressure 26.210s 1.360ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.260s 1.200ms 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.129ms 1 1 100.00
hmac_test_sha512_vectors 18.630s 420.389us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 887.308us 1 1 100.00
hmac_test_hmac384_vectors 6.280s 222.586us 1 1 100.00
hmac_test_hmac512_vectors 10.110s 1.378ms 1 1 100.00
V2 burst_wr hmac_burst_wr 16.930s 1.955ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.737m 4.431ms 1 1 100.00
V2 error hmac_error 53.920s 22.266ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 54.100s 7.713ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.630s 3.770ms 1 1 100.00
hmac_long_msg 44.230s 1.170ms 1 1 100.00
hmac_back_pressure 26.210s 1.360ms 1 1 100.00
hmac_datapath_stress 1.737m 4.431ms 1 1 100.00
hmac_burst_wr 16.930s 1.955ms 1 1 100.00
hmac_stress_all 52.320s 5.716ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.630s 3.770ms 1 1 100.00
hmac_long_msg 44.230s 1.170ms 1 1 100.00
hmac_back_pressure 26.210s 1.360ms 1 1 100.00
hmac_datapath_stress 1.737m 4.431ms 1 1 100.00
hmac_wipe_secret 54.100s 7.713ms 1 1 100.00
hmac_test_sha256_vectors 7.260s 1.200ms 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.129ms 1 1 100.00
hmac_test_sha512_vectors 18.630s 420.389us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 887.308us 1 1 100.00
hmac_test_hmac384_vectors 6.280s 222.586us 1 1 100.00
hmac_test_hmac512_vectors 10.110s 1.378ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.630s 3.770ms 1 1 100.00
hmac_long_msg 44.230s 1.170ms 1 1 100.00
hmac_back_pressure 26.210s 1.360ms 1 1 100.00
hmac_datapath_stress 1.737m 4.431ms 1 1 100.00
hmac_burst_wr 16.930s 1.955ms 1 1 100.00
hmac_error 53.920s 22.266ms 1 1 100.00
hmac_wipe_secret 54.100s 7.713ms 1 1 100.00
hmac_test_sha256_vectors 7.260s 1.200ms 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.129ms 1 1 100.00
hmac_test_sha512_vectors 18.630s 420.389us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 887.308us 1 1 100.00
hmac_test_hmac384_vectors 6.280s 222.586us 1 1 100.00
hmac_test_hmac512_vectors 10.110s 1.378ms 1 1 100.00
hmac_stress_all 52.320s 5.716ms 1 1 100.00
V2 stress_all hmac_stress_all 52.320s 5.716ms 1 1 100.00
V2 alert_test hmac_alert_test 0.560s 15.040us 1 1 100.00
V2 intr_test hmac_intr_test 0.600s 13.524us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.760s 350.772us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.760s 350.772us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.890s 201.799us 1 1 100.00
hmac_csr_rw 0.770s 18.232us 1 1 100.00
hmac_csr_aliasing 5.210s 162.484us 1 1 100.00
hmac_same_csr_outstanding 1.810s 706.296us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.890s 201.799us 1 1 100.00
hmac_csr_rw 0.770s 18.232us 1 1 100.00
hmac_csr_aliasing 5.210s 162.484us 1 1 100.00
hmac_same_csr_outstanding 1.810s 706.296us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.850s 733.482us 1 1 100.00
hmac_tl_intg_err 2.460s 185.516us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.460s 185.516us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.630s 3.770ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.690s 747.922us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 55.090s 4.941ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.690s 119.938us 1 1 100.00
TOTAL 28 28 100.00