I2C Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	12.530s	9.800ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	17.030s	1.669ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.010s	64.661us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.910s	25.993us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.080s	234.973us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.280s	47.105us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.940s	74.987us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.910s	25.993us	1	1	100.00
		i2c_csr_aliasing	1.280s	47.105us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.020s	252.479us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	49.012m	108.968ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	6.940s	1.011ms	1	1	100.00
V2	host_override	i2c_host_override	0.820s	49.548us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.339m	10.460ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	34.870s	1.835ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.970s	136.419us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.660s	553.376us	1	1	100.00
		i2c_host_fifo_reset_rx	11.710s	227.269us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	38.100s	9.523ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	29.390s	1.627ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.930s	135.601us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.290s	1.009ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	50.720s	37.994ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.820s	2.540ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	15.140s	1.235ms	1	1	100.00
		i2c_target_intr_smoke	5.450s	2.316ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.120s	211.919us	1	1	100.00
		i2c_target_fifo_reset_tx	0.880s	202.418us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	15.580s	25.708ms	1	1	100.00
		i2c_target_stress_rd	15.140s	1.235ms	1	1	100.00
		i2c_target_intr_stress_wr	56.740s	14.920ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.870s	1.065ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.060s	1.919ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.500s	1.670ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	1.750s	281.432us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.730s	1.507ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.230s	458.754us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	6.940s	1.011ms	1	1	100.00
		i2c_host_perf_precise	1.370s	64.086us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	29.390s	1.627ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.350s	156.961us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.170s	2.478ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.670s	718.776us	1	1	100.00
		i2c_target_nack_txstretch	1.150s	607.700us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.320s	941.253us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.650s	915.788us	1	1	100.00
V2	alert_test	i2c_alert_test	0.650s	23.427us	1	1	100.00
V2	intr_test	i2c_intr_test	0.980s	18.539us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.750s	126.560us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.750s	126.560us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.010s	64.661us	1	1	100.00
		i2c_csr_rw	0.910s	25.993us	1	1	100.00
		i2c_csr_aliasing	1.280s	47.105us	1	1	100.00
		i2c_same_csr_outstanding	1.080s	377.572us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.010s	64.661us	1	1	100.00
		i2c_csr_rw	0.910s	25.993us	1	1	100.00
		i2c_csr_aliasing	1.280s	47.105us	1	1	100.00
		i2c_same_csr_outstanding	1.080s	377.572us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.600s	441.641us	1	1	100.00
		i2c_sec_cm	1.020s	81.953us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.600s	441.641us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.610s	2.293ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.310s	549.446us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.270s	662.697us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.37454752268440334528968733476847636179267712784528208804169858767667664006224
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 252479216 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 252479216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.85219014894490012774111719947922024113627547566085534877865377142024090134335
      Line 145, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 108967548755 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 108967548755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.4810795936523732597982673289061362188196683779596761104514697254127444400750
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2293485379 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2293485379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.11481500588507384307798409702129658265671240218852871419572084122687735213018
      Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 662697035 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 662697035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.45283996996742225221773454706724595757432825592267652894465580104967511419242
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1009250020 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1009250020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.88323828069571496083424443709943542311363395435341527921025844712612111197559
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 549445619 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 194 [0xc2])
        UVM_INFO @ 549445619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.75532856402146232352107811172199295482287138865053388854560831460635183512992
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 135601311 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @33688
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.39556732722830510610949180071959868356649255386088529555100574485156216233365
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 607700303 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 607700303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---