KEYMGR Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	6.580s	512.910us	1	1	100.00
V1	random	keymgr_random	3.240s	591.865us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.330s	39.169us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.800s	208.328us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.530s	2.149ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.980s	386.171us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.430s	105.719us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.800s	208.328us	1	1	100.00
		keymgr_csr_aliasing	9.980s	386.171us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.007m	15.385ms	1	1	100.00
V2	sideload	keymgr_sideload	2.250s	195.237us	1	1	100.00
		keymgr_sideload_kmac	5.280s	782.415us	1	1	100.00
		keymgr_sideload_aes	2.060s	34.363us	1	1	100.00
		keymgr_sideload_otbn	7.320s	1.421ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.690s	111.859us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.040s	93.741us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.870s	74.893us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.420s	167.524us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.080s	365.381us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.980s	113.012us	1	1	100.00
V2	stress_all	keymgr_stress_all	21.010s	878.398us	1	1	100.00
V2	intr_test	keymgr_intr_test	0.840s	28.807us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.860s	15.645us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.670s	66.750us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.670s	66.750us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.330s	39.169us	1	1	100.00
		keymgr_csr_rw	0.800s	208.328us	1	1	100.00
		keymgr_csr_aliasing	9.980s	386.171us	1	1	100.00
		keymgr_same_csr_outstanding	2.060s	42.578us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.330s	39.169us	1	1	100.00
		keymgr_csr_rw	0.800s	208.328us	1	1	100.00
		keymgr_csr_aliasing	9.980s	386.171us	1	1	100.00
		keymgr_same_csr_outstanding	2.060s	42.578us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
		keymgr_tl_intg_err	2.380s	563.636us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	1.510s	387.092us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	1.510s	387.092us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	1.510s	387.092us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	1.510s	387.092us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.430s	404.233us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.380s	563.636us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	1.510s	387.092us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.007m	15.385ms	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.240s	591.865us	1	1	100.00
		keymgr_csr_rw	0.800s	208.328us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.240s	591.865us	1	1	100.00
		keymgr_csr_rw	0.800s	208.328us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.240s	591.865us	1	1	100.00
		keymgr_csr_rw	0.800s	208.328us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.040s	93.741us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.080s	365.381us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.080s	365.381us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.240s	591.865us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.140s	348.507us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.270s	48.177us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.040s	93.741us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.270s	48.177us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.270s	48.177us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.270s	48.177us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.780s	723.961us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.270s	48.177us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.110s	165.829us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.77504078153605897823391189353247218719943611400375182400580483139706651386579
      Line 129, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 165829146 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 165829146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---