| V1 |
smoke |
kmac_smoke |
16.510s |
2.228ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.070s |
24.362us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.140s |
31.986us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
10.670s |
1.497ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
6.770s |
494.161us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.560s |
108.505us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.140s |
31.986us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.770s |
494.161us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.730s |
43.585us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.340s |
66.437us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
4.055m |
11.914ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
3.588m |
22.556ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
39.320s |
4.125ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
24.560m |
108.575ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
24.100m |
69.795ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
13.380s |
4.365ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
27.986m |
86.908ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.895m |
79.388ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
2.840s |
127.919us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.650s |
321.395us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
21.580s |
1.493ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
2.715m |
4.062ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
4.162m |
26.341ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.146m |
6.359ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
1.004m |
2.210ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
6.270s |
7.208ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
6.720s |
331.036us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.040s |
75.224us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.150s |
62.377us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
13.830s |
3.719ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.380s |
42.054us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
11.643m |
13.824ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.070s |
19.703us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
0.940s |
14.704us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.470s |
371.164us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.470s |
371.164us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.070s |
24.362us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.140s |
31.986us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.770s |
494.161us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.020s |
58.023us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.070s |
24.362us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.140s |
31.986us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
6.770s |
494.161us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.020s |
58.023us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.340s |
121.698us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.340s |
121.698us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.340s |
121.698us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.340s |
121.698us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.910s |
399.670us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
1.095m |
9.918ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.780s |
212.382us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.780s |
212.382us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.380s |
42.054us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
16.510s |
2.228ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
21.580s |
1.493ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.340s |
121.698us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
1.095m |
9.918ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
1.095m |
9.918ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
1.095m |
9.918ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
16.510s |
2.228ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.380s |
42.054us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
1.095m |
9.918ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
50.130s |
2.182ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
16.510s |
2.228ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
2.044m |
4.853ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |