0fc384d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 59.000s | 10.989ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 7.000s | 41.333us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 6.000s | 12.916us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 275.567us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 2.000s | 61.944us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 2.000s | 24.864us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 6.000s | 12.916us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 2.000s | 61.944us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 9.000s | 1.525ms | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 3.000s | 114.088us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 37.000s | 3.886ms | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 10.000s | 2.949ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 2.000s | 58.601us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 8.000s | 35.981us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 10.000s | 43.426us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 10.000s | 43.426us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 7.000s | 41.333us | 1 | 1 | 100.00 |
| mbx_csr_rw | 6.000s | 12.916us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 61.944us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 52.319us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 7.000s | 41.333us | 1 | 1 | 100.00 |
| mbx_csr_rw | 6.000s | 12.916us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 61.944us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 52.319us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 6 | 8 | 75.00 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 8.000s | 84.174us | 1 | 1 | 100.00 |
| mbx_sec_cm | 1.000s | 35.791us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 14 | 16 | 87.50 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress.11656486280166877977881263733786218802041130622979974834734701418018166575677
Line 428, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 1525310667 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 1525310667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,287): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:
0.mbx_stress_zero_delays.13684422978420956154721291555782452208518578717780328807375644875510597790166
Line 229, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,287): (time 114087545 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 114087545 ps: (mbx_ombx.sv:287) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 114087545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---