RV_TIMER Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.600s	39.824us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.690s	58.472us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.840s	13.297us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.270s	176.164us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.670s	19.882us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.160s	57.579us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.840s	13.297us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	19.882us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.860s	131.327us	0	1	0.00
V2	disabled	rv_timer_disabled	1.250s	2.652ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	48.250s	35.287ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	48.250s	35.287ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.150s	1.337ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.550s	29.935us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.790s	12.919us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.890s	688.871us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.890s	688.871us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.690s	58.472us	1	1	100.00
		rv_timer_csr_rw	0.840s	13.297us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	19.882us	1	1	100.00
		rv_timer_same_csr_outstanding	0.680s	62.546us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.690s	58.472us	1	1	100.00
		rv_timer_csr_rw	0.840s	13.297us	1	1	100.00
		rv_timer_csr_aliasing	0.670s	19.882us	1	1	100.00
		rv_timer_same_csr_outstanding	0.680s	62.546us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.900s	113.284us	1	1	100.00
		rv_timer_tl_intg_err	1.040s	142.686us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.040s	142.686us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.780s	63.318us	0	1	0.00
V3	max_value	rv_timer_max	1.680s	175.281us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	26.230s	3.233ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.47199620797913461447737543891665736229886639654918171430836804216663983802542
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @  63317657 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6e9bdd04) == 0x1
        UVM_INFO @  63317657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.4024308147735197911739178247636339828359006377161327239623216384604804933632
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 131327156 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x4e5d9704) == 0x1
        UVM_INFO @ 131327156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.25543223325226044932061473423067457038200529674652125226988860379273564273833
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 175281451 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
        UVM_INFO @ 175281451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---