SPI_DEVICE/1R1W Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	32.360s	9.360ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.980s	269.873us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.190s	91.879us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.560s	7.499ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.460s	592.119us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.860s	392.403us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.190s	91.879us	1	1	100.00
		spi_device_csr_aliasing	16.460s	592.119us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.960s	46.184us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.700s	86.497us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.890s	47.720us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.720s	1.215us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.750s	5.434us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.780s	488.681us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.780s	488.681us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.510s	3.503ms	1	1	100.00
		spi_device_tpm_sts_read	0.770s	31.806us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	28.020s	22.232ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.170s	5.812ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.280s	503.181us	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.280s	503.181us	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	15.780s	24.730ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	15.780s	24.730ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	15.780s	24.730ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	15.780s	24.730ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	15.780s	24.730ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.340s	1.168ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.310s	2.110ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.310s	2.110ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.310s	2.110ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.660s	213.503us	1	1	100.00
		spi_device_read_buffer_direct	11.920s	2.239ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.310s	2.110ms	1	1	100.00
		spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	4.168m	209.008ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.770s	384.452us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.770s	384.452us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	32.360s	9.360ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.444m	22.630ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.816m	7.504ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.950s	36.897us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.840s	14.072us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.930s	50.021us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.930s	50.021us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.980s	269.873us	1	1	100.00
		spi_device_csr_rw	2.190s	91.879us	1	1	100.00
		spi_device_csr_aliasing	16.460s	592.119us	1	1	100.00
		spi_device_same_csr_outstanding	2.370s	86.854us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.980s	269.873us	1	1	100.00
		spi_device_csr_rw	2.190s	91.879us	1	1	100.00
		spi_device_csr_aliasing	16.460s	592.119us	1	1	100.00
		spi_device_same_csr_outstanding	2.370s	86.854us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.330s	382.867us	1	1	100.00
		spi_device_tl_intg_err	9.210s	201.699us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.210s	201.699us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.260s	703.855us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.80276488041690735549799601904671370451645467549851110049753963814412323228219
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1023395 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[77])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1023395 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1023395 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[973])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.15975153960533180184330430015798241369351056459440294167296905646887028134072
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3138471 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfe0751 [111111100000011101010001] vs 0x0 [0])
        UVM_ERROR @   3176471 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3d3eeb [1111010011111011101011] vs 0x0 [0])
        UVM_ERROR @   3266471 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc192b0 [110000011001001010110000] vs 0x0 [0])
        UVM_ERROR @   3312471 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x837dc [10000011011111011100] vs 0x0 [0])
        UVM_ERROR @   3323471 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb34f83 [101100110100111110000011] vs 0x0 [0])