SRAM_CTRL/MAIN Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.520s	544.043us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.910s	40.164us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.820s	48.514us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.320s	130.604us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.830s	19.021us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.340s	1.272ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.820s	48.514us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	19.021us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.709m	2.690ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.873m	8.870ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.135m	12.035ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.288m	13.715ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.170m	179.770ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	13.090m	72.360ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	41.600s	18.278ms	1	1	100.00
V2	executable	sram_ctrl_executable	49.620s	9.417ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.150s	5.363ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.069m	58.166ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.170s	2.903ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.910s	2.702ms	1	1	100.00
		sram_ctrl_throughput_w_readback	26.010s	859.265us	1	1	100.00
V2	regwen	sram_ctrl_regwen	1.696m	2.013ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.490s	1.390ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	46.210m	383.003ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.030s	83.105us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.480s	236.818us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.480s	236.818us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.910s	40.164us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	48.514us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	19.021us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.010s	23.893us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.910s	40.164us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	48.514us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	19.021us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.010s	23.893us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	35.310s	7.332ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
		sram_ctrl_tl_intg_err	1.540s	119.354us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.540s	119.354us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	1.696m	2.013ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	1.696m	2.013ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.820s	48.514us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	49.620s	9.417ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	49.620s	9.417ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	49.620s	9.417ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	41.600s	18.278ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.360s	2.660ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	35.310s	7.332ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.050s	662.574us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.520s	544.043us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.520s	544.043us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	49.620s	9.417ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	41.600s	18.278ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.520s	544.043us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.960s	11.910us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	22.370s	4.346ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.36124090671792589181455063878551313853300785714313728693375908764609542182149
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 662574088 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x64) != exp (0x53)
        UVM_INFO @ 662574088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.5056700651148041975509286145426430361924434026128999457871711811248886380887
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  11910183 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  11910183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---