UART Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.810s	557.986us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.570s	17.657us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.730s	15.018us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.390s	486.217us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.890s	275.055us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.290s	93.112us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.730s	15.018us	1	1	100.00
		uart_csr_aliasing	0.890s	275.055us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.451m	106.593ms	1	1	100.00
V2	parity	uart_smoke	1.810s	557.986us	1	1	100.00
		uart_tx_rx	1.451m	106.593ms	1	1	100.00
V2	parity_error	uart_intr	7.520s	10.990ms	1	1	100.00
		uart_rx_parity_err	30.470s	23.539ms	1	1	100.00
V2	watermark	uart_tx_rx	1.451m	106.593ms	1	1	100.00
		uart_intr	7.520s	10.990ms	1	1	100.00
V2	fifo_full	uart_fifo_full	21.730s	75.557ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	53.190s	89.732ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.053m	64.423ms	1	1	100.00
V2	rx_frame_err	uart_intr	7.520s	10.990ms	1	1	100.00
V2	rx_break_err	uart_intr	7.520s	10.990ms	1	1	100.00
V2	rx_timeout	uart_intr	7.520s	10.990ms	1	1	100.00
V2	perf	uart_perf	10.709m	20.075ms	1	1	100.00
V2	sys_loopback	uart_loopback	22.400s	8.783ms	1	1	100.00
V2	line_loopback	uart_loopback	22.400s	8.783ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	49.430s	40.082ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.120s	4.516ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	13.590s	6.676ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.830s	4.640ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.309m	150.374ms	1	1	100.00
V2	stress_all	uart_stress_all	44.220s	287.597ms	1	1	100.00
V2	alert_test	uart_alert_test	0.860s	11.187us	1	1	100.00
V2	intr_test	uart_intr_test	0.760s	11.238us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.560s	99.190us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.560s	99.190us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.570s	17.657us	1	1	100.00
		uart_csr_rw	0.730s	15.018us	1	1	100.00
		uart_csr_aliasing	0.890s	275.055us	1	1	100.00
		uart_same_csr_outstanding	0.840s	55.595us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.570s	17.657us	1	1	100.00
		uart_csr_rw	0.730s	15.018us	1	1	100.00
		uart_csr_aliasing	0.890s	275.055us	1	1	100.00
		uart_same_csr_outstanding	0.840s	55.595us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.050s	756.529us	1	1	100.00
		uart_tl_intg_err	1.070s	689.868us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.070s	689.868us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	53.610s	12.519ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.17053406208969158148261545523527221648243418940483694033558789788003997056305
      Line 75, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 39287344899 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
        UVM_ERROR @ 39287355103 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 39287365307 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (35 [0x23] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 39287375511 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 39287385715 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (35 [0x23] vs 255 [0xff]) reg name: uart_reg_block.rdata