CHIP Simulation Results

Tuesday October 14 2025 16:09:07 UTC

GitHub Revision: `0fc384d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.733m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.733m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.825s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.747s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	13.258s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.596m	6.650ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.596m	6.650ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.596m	6.650ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	34.210s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.194m		0	1	0.00
		chip_sw_example_concurrency	5.342m	3.960ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.948s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.990s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	11.210s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	11.210s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.870s	57.482us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.121m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.127m	8.680ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.527m	4.494ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	13.543s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.129s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	12.511s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	13.098s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.970s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.970s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.031m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.795m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.039m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.039m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.853m	2.963ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.892m	4.243ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.712m	14.168ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.357s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.030s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	19.220m	25.084ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.466m	4.493ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.401m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.401m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.884s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.461m	3.703ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.461m	3.703ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.887m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.659m	3.352ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.939m	5.396ms	1	1	100.00
		chip_sw_aes_idle	3.746m	3.615ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.832m	4.309ms	1	1	100.00
		chip_sw_kmac_idle	4.795m	4.548ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.414m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.674m	11.731ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	13.490m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.036m	12.018ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.588s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.418s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.612s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.828s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.130s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.318s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.588s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.418s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.612s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.828s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.130s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.318s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.483s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.680s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.180s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.930s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.640s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.123s		0	1	0.00
		chip_sw_clkmgr_jitter	3.388m	3.639ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.788m	5.808ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.946s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	40.400s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	39.350s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	43.480s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	40.040s	10.240us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.160s	10.360us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.208s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.577s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.961s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.572s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.714m	11.625ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.461m	3.703ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.612s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.714m	11.625ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.527s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.795s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.028s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.469s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.154s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.712m	14.168ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	26.653m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.254m	9.581ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.805m	9.810ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.648m	5.309ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.437s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.866s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.505s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.805m	9.810ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.870s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.827s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.380s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	13.113s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.774s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.752s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.866s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.279s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.408m	10.047ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.054s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.150s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.736s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.836s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.367m	10.011ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.372m	11.980ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.755s		0	1	0.00
		chip_prim_tl_access	10.351m	13.633ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.588s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.418s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.612s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.828s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.757s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.130s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.318s		0	1	0.00
		chip_rv_dm_lc_disabled	19.220m	25.084ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.314m	4.973ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.680s	10.100us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.820m	4.094ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.746m	3.615ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.265m	5.193ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	38.180s	10.380us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.832m	4.309ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.960m	4.862ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.902m	6.309ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	38.640s	10.300us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.367m	10.011ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.970s	10.300us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.854m	4.013ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.795m	4.548ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.291s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.291s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.881s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.243m	3.599ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.928s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.367m	10.011ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.930s	10.180us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.664s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.483s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.939m	5.396ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.939m	5.396ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.939m	5.396ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.301m	5.600ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.372m	11.980ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.372m	11.980ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.656m	9.151ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.123s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.755s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.039m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.301m	5.600ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.367m	10.011ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.656m	9.151ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.041m	4.987ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.301m	5.600ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.367m	10.011ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.656m	9.151ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.041m	4.987ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.134s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.279s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.054s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.150s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.736s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.836s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.606s		0	1	0.00
		chip_prim_tl_access	10.351m	13.633ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	10.351m	13.633ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.394s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.391s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.577s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.483s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.680s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	38.180s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	57.930s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	38.640s	10.300us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.123s		0	1	0.00
		chip_sw_clkmgr_jitter	3.388m	3.639ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	9.863m	9.910ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	9.863m	9.910ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.772m	3.865ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.102m	4.861ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.221m	3.787ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.849m	6.203ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.599m	4.540ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.936m	4.108ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	5.041m	4.987ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	26.653m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	26.653m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.594m	4.788ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.536m	3.996ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.221m	3.464ms	1	1	100.00
		chip_sw_csrng_smoketest	3.429m	3.148ms	1	1	100.00
		chip_sw_gpio_smoketest	3.501m	3.738ms	1	1	100.00
		chip_sw_hmac_smoketest	5.302m	5.505ms	1	1	100.00
		chip_sw_kmac_smoketest	4.772m	4.454ms	1	1	100.00
		chip_sw_otbn_smoketest	5.162m	5.105ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.760m	5.675ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.069m	4.550ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.462m	5.962ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.035m	4.921ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.768m	5.500ms	1	1	100.00
		chip_sw_uart_smoketest	3.806m	4.380ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.474s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.948s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.121m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	14.651s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.647m	5.114ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.131m	5.275ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	42.839m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	5.822m	6.031ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.006s		0	1	0.00
		chip_rv_dm_lc_disabled	19.220m	25.084ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.608s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.444s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.534s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.651s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.006s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.570s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.804s		0	1	0.00
		rom_volatile_raw_unlock	12.717s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.728s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	55.515s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	53.219s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.465m	4.256ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.465m	4.256ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	11.210s		0	1	0.00
		chip_same_csr_outstanding	9.780s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	11.210s		0	1	0.00
		chip_same_csr_outstanding	9.780s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	46.950s	36.617us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.130s	12.418us	1	1	100.00
		xbar_smoke_large_delays	4.728m	2.390ms	1	1	100.00
		xbar_smoke_slow_rsp	5.085m	1.785ms	1	1	100.00
		xbar_random_zero_delays	56.380s	47.837us	1	1	100.00
		xbar_random_large_delays	10.757m	5.485ms	1	1	100.00
		xbar_random_slow_rsp	22.483m	7.921ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.015m	36.968us	1	1	100.00
		xbar_error_and_unmapped_addr	59.140s	41.879us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.322m	210.290us	1	1	100.00
		xbar_error_and_unmapped_addr	59.140s	41.879us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.852m	890.120us	1	1	100.00
		xbar_access_same_device_slow_rsp	54.556m	21.350ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	29.310s	27.124us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.252m	613.955us	1	1	100.00
		xbar_stress_all_with_error	4.300m	242.369us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.604m	1.145ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.030m	30.406us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.326s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	14.362s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.181s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.287s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.696s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.112s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.083s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.182s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.299s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	12.002s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.900s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	14.633s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.575s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.051m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.094m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	55.017s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.019m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.068m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	59.978s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	50.728s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	55.412s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	45.482s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	58.829s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	42.672s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	49.582s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	35.526s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	33.400s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	25.008s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.944s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.571s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.060s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.565s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.464s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.605s		0	1	0.00
		rom_e2e_asm_init_dev	12.534s		0	1	0.00
		rom_e2e_asm_init_prod	12.790s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.789s		0	1	0.00
		rom_e2e_asm_init_rma	13.178s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.509s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.036s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.907s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.188s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.319m	4.899ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.076m	5.844ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.691s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.785s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.406s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.291s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	23.028m	16.636ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.613s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	21.026m	12.928ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.829s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.210s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.691s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.785s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.406s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.399s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.637s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.535s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.356s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	25.518m	16.181ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.691m	3.617ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.102m	4.316ms	1	1	100.00
		chip_plic_all_irqs_0	10.483m	5.371ms	1	1	100.00
		chip_plic_all_irqs_10	10.425m	7.704ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.975m	3.684ms	1	1	100.00
		chip_sw_dma_abort	4.060m	5.412ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.916s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.056s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.805s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.071s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.743s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.880s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.232s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.243s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.179s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.283s		0	1	0.00
		chip_sw_entropy_src_smoketest	3.808m	3.431ms	1	1	100.00
		chip_sw_mbx_smoketest	5.261m	4.806ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.84577083816206263829282891632042835063503565869331638739030878053778741539569
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.116s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.29546380845147900349572593722446718124863994322598331257581922418831819406791
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 109.449s, Critical Path: 0.04s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.65209056812335328992027373864540229236729453771966443288726318524543610435889
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 109.790s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.112725341662443576705900811828908981101273555772764354606035063397381778838222
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 96.772s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.95519281791123492550076117011574662313696401251727799903380008897583674818884
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 93.327s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.89023760593407098772553897415014251907272896192847750340467306315358794284289
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.114998194217476074819163572764291211281943948726756902111269556640483099895932
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.77678034682176116182234117872903934675364644039867366502523927709998552445785
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.30181986779039765181681929475666545551303258714140170558205416160505452196465
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.57048006348992303746605481606765478568723523847150341430248631293025091235553
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.51318228443004657795599028631716495340291192097331616046862050825049102103535
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.107321770040648536049853378410400003555699703527768493945043618368206633541923
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.18100609003109145081300881878833157414210189471760819765382940580371162556408
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.47472205476359120792128145379110732979691189864415343528710745289441356127834
Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.470334 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.470334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.38683825027154218430365462710800864597336801073598865822572013916629293352201
Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.830689 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.830689 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.16797533492509804376156990733664106032854746161338884338762305541154897756014
Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.576976 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.576976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.74025306963907738970261479546272148862428666361980939361997219740781835425466
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.874325 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.874325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.3974705775573662875963789793014529934007040670724949403238627165921805869664
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.610779 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.610779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.112751487416565552658691779424687588747716266821320728519840215421373700795377
Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12018.493247 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.493247 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.21164618515204247790363908488283885061794854901547769191124573190565751870190
Line 406, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10010.826560 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5100963818007039495091384604749199639052230338208238031984108212838017434877225744860667698772790936428585570945079911363306171305002268907050192628702300 [0x6164fde4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3e7324d157f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 10010.826560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.103966217050843236566559657055267501112809744793723017395192350894897806821803
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10047.178993 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (8550359024362554199136835527144969070078097012098306869394001914585705320090912153218794445928941834765942643319693782858846917728543701067171143136664668 [0xa34148c9aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd32517f8387f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 10047.178993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.23590100516017937492856244504350135401464655184480906325258120116476462410697
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 2962.695232 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h5a9e1438  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h32  a_opcode: 'h0  a_user: 'h26958  d_param: 'h0  d_source: 'h32  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2962.695232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.52461492533538628720174283461481265246782751520471224546377737069380692149561
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4243.304466 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'he51ab801  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h0  a_user: 'h26950  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4243.304466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.35045962200002373773295876097582631126591807033539127306284951958827706374186
    Line 1365, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.36488181631663211598674133458062718379410046363197477702169761553837722960220
    Line 415, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4494.242448 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4494.242448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_test_locked0_to_scrap.16285901700473014438118279044163052504247201372384217790464573465358259823180
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.107815990615344559566397391973242366760659333492657001937677758582175193363574
    Line 636, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9810.478568 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9810.478568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.15233692518987083912445772991227841239727302222457851683689176669675044101582
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3864.814372 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3864.814372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.57665798806110674442016491750796907750577760169092016739696466328270694128404
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4861.114832 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4861.114832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.29285491945170119641059257873798987225842757939697767976467429390767118815515
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3702.666387 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3702.666387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.85120388271586409492384123668705984175811838051841953945145790244803878302620
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4539.986664 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4539.986664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.76212689959553687856732639194584759642639010030959403654635174213863359512624
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6203.189012 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6203.189012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.108078591495802043921910603979015423974055100936212261770031324997099416697112
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.35962756822168825912403226283978725999335121511096882402911652775917150548928
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4256.232302 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4256.232302 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.58902980616599170062895402071146789714548845309958390491610114548495696334976
    Line 376, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14167.919804 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14167.919804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.111821699463788271707612116814850926413842361756118034541684066009059416115432
    Line 257, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 25083.922129 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x404e0 read out mismatch
  UVM_INFO @ 25083.922129 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.89396499130587373601190201203167265788144121828930878263630906775616985188275
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.103179732121823878560385121327765746716015652474841858315684487343833687720385
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5412.075864 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5412.075864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```