AES/MASKED Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	107.105us	1	1	100.00
V1	smoke	aes_smoke	3.000s	62.901us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	63.930us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	66.338us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	2.218ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	146.640us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	187.395us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	66.338us	1	1	100.00
		aes_csr_aliasing	3.000s	146.640us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	62.901us	1	1	100.00
		aes_config_error	3.000s	352.735us	1	1	100.00
		aes_stress	5.000s	272.287us	1	1	100.00
V2	key_length	aes_smoke	3.000s	62.901us	1	1	100.00
		aes_config_error	3.000s	352.735us	1	1	100.00
		aes_stress	5.000s	272.287us	1	1	100.00
V2	back2back	aes_stress	5.000s	272.287us	1	1	100.00
		aes_b2b	3.000s	144.683us	1	1	100.00
V2	backpressure	aes_stress	5.000s	272.287us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	62.901us	1	1	100.00
		aes_config_error	3.000s	352.735us	1	1	100.00
		aes_stress	5.000s	272.287us	1	1	100.00
		aes_alert_reset	3.000s	171.975us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	72.150us	1	1	100.00
		aes_config_error	3.000s	352.735us	1	1	100.00
		aes_alert_reset	3.000s	171.975us	1	1	100.00
V2	trigger_clear_test	aes_clear	7.000s	268.077us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	383.096us	1	1	100.00
V2	reset_recovery	aes_alert_reset	3.000s	171.975us	1	1	100.00
V2	stress	aes_stress	5.000s	272.287us	1	1	100.00
V2	sideload	aes_stress	5.000s	272.287us	1	1	100.00
		aes_sideload	3.000s	114.757us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	146.305us	1	1	100.00
V2	stress_all	aes_stress_all	41.000s	8.505ms	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	63.881us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	90.798us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	90.798us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	63.930us	1	1	100.00
		aes_csr_rw	2.000s	66.338us	1	1	100.00
		aes_csr_aliasing	3.000s	146.640us	1	1	100.00
		aes_same_csr_outstanding	2.000s	126.684us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	63.930us	1	1	100.00
		aes_csr_rw	2.000s	66.338us	1	1	100.00
		aes_csr_aliasing	3.000s	146.640us	1	1	100.00
		aes_same_csr_outstanding	2.000s	126.684us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	242.348us	1	1	100.00
V2S	fault_inject	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	451.555us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	1.874ms	1	1	100.00
		aes_tl_intg_err	3.000s	170.775us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	170.775us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	3.000s	171.975us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	62.901us	1	1	100.00
		aes_stress	5.000s	272.287us	1	1	100.00
		aes_alert_reset	3.000s	171.975us	1	1	100.00
		aes_core_fi	3.000s	190.633us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	125.647us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	66.338us	1	1	100.00
		aes_stress	5.000s	272.287us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	272.287us	1	1	100.00
		aes_sideload	3.000s	114.757us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	66.338us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	66.338us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	66.338us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	66.338us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	66.338us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	272.287us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	272.287us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	507.866us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	507.866us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	3.000s	89.038us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	507.866us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	3.000s	171.975us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	3.000s	65.605us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	507.866us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	3.000s	89.038us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.000s	82.172us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.46756719033810582232471998053257021974479819146166447388492423885687270180299
      Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.86621757060257462037779017198681402502070679529599176068627952741071008138565
      Line 193, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  82171849 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  82171849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---