DMA Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	308.604us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	3.000s	730.653us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.000s	1.145ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	19.613us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	47.294us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	152.794us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	1.143ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	384.631us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	47.294us	1	1	100.00
		dma_csr_aliasing	7.000s	1.143ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	55.000s	18.249ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	2.517m	25.066ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	8.450m	165.559ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	8.450m	165.559ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.517m	25.066ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	13.933m	83.235ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	8.450m	165.559ms	1	1	100.00
V2	dma_abort	dma_abort	20.000s	6.143ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.217m	23.504ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	34.449us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	67.376us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	61.768us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	61.768us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	19.613us	1	1	100.00
		dma_csr_rw	1.000s	47.294us	1	1	100.00
		dma_csr_aliasing	7.000s	1.143ms	1	1	100.00
		dma_same_csr_outstanding	3.000s	2.296ms	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	19.613us	1	1	100.00
		dma_csr_rw	1.000s	47.294us	1	1	100.00
		dma_csr_aliasing	7.000s	1.143ms	1	1	100.00
		dma_same_csr_outstanding	3.000s	2.296ms	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	99.664us	1	1	100.00
		dma_generic_stress	13.933m	83.235ms	1	1	100.00
		dma_handshake_stress	8.450m	165.559ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	2.911ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.000s	109.815us	1	1	100.00
		dma_sec_cm	2.000s	11.640us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	2.400m	16.325ms	1	1	100.00
		dma_longer_transfer	4.000s	685.233us	1	1	100.00
		dma_stress_all_with_rand_reset	17.000s	9.161ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.41021411411961052195033700997456191074654004653702094720285443904123021196012
      Line 131, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9161127833ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9161127833ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---