EDN Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.910s 17.192us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.900s 64.766us 1 1 100.00
V1 csr_rw edn_csr_rw 0.790s 66.008us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.530s 1.633ms 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.160s 35.627us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.970s 37.777us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.790s 66.008us 1 1 100.00
edn_csr_aliasing 1.160s 35.627us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.190s 142.887us 1 1 100.00
V2 csrng_commands edn_genbits 1.190s 142.887us 1 1 100.00
V2 genbits edn_genbits 1.190s 142.887us 1 1 100.00
V2 interrupts edn_intr 0.940s 28.521us 1 1 100.00
V2 alerts edn_alert 0.970s 76.144us 1 1 100.00
V2 errs edn_err 0.950s 54.529us 1 1 100.00
V2 disable edn_disable 0.780s 12.105us 1 1 100.00
edn_disable_auto_req_mode 0.970s 29.090us 1 1 100.00
V2 stress_all edn_stress_all 1.610s 83.421us 1 1 100.00
V2 intr_test edn_intr_test 0.750s 25.057us 1 1 100.00
V2 alert_test edn_alert_test 0.840s 15.340us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 1.810s 123.215us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 1.810s 123.215us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.900s 64.766us 1 1 100.00
edn_csr_rw 0.790s 66.008us 1 1 100.00
edn_csr_aliasing 1.160s 35.627us 1 1 100.00
edn_same_csr_outstanding 1.260s 181.433us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.900s 64.766us 1 1 100.00
edn_csr_rw 0.790s 66.008us 1 1 100.00
edn_csr_aliasing 1.160s 35.627us 1 1 100.00
edn_same_csr_outstanding 1.260s 181.433us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.170s 4.204ms 1 1 100.00
edn_tl_intg_err 1.270s 176.131us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.830s 17.996us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 0.970s 76.144us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.170s 4.204ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.170s 4.204ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.170s 4.204ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.170s 4.204ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 0.970s 76.144us 1 1 100.00
edn_sec_cm 4.170s 4.204ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 0.970s 76.144us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.270s 176.131us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets