HMAC Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.340s 208.181us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.880s 252.089us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.690s 23.661us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.780s 3.775ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.440s 635.161us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.973m 16.028ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.690s 23.661us 1 1 100.00
hmac_csr_aliasing 5.440s 635.161us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 52.250s 1.195ms 1 1 100.00
V2 back_pressure hmac_back_pressure 53.850s 1.164ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.660s 191.865us 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.843ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 259.256us 1 1 100.00
hmac_test_hmac256_vectors 6.190s 850.969us 1 1 100.00
hmac_test_hmac384_vectors 9.820s 640.913us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 715.796us 1 1 100.00
V2 burst_wr hmac_burst_wr 23.310s 1.240ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.684m 6.511ms 1 1 100.00
V2 error hmac_error 49.380s 3.722ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 54.060s 5.712ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.340s 208.181us 1 1 100.00
hmac_long_msg 52.250s 1.195ms 1 1 100.00
hmac_back_pressure 53.850s 1.164ms 1 1 100.00
hmac_datapath_stress 2.684m 6.511ms 1 1 100.00
hmac_burst_wr 23.310s 1.240ms 1 1 100.00
hmac_stress_all 5.024m 52.845ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.340s 208.181us 1 1 100.00
hmac_long_msg 52.250s 1.195ms 1 1 100.00
hmac_back_pressure 53.850s 1.164ms 1 1 100.00
hmac_datapath_stress 2.684m 6.511ms 1 1 100.00
hmac_wipe_secret 54.060s 5.712ms 1 1 100.00
hmac_test_sha256_vectors 7.660s 191.865us 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.843ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 259.256us 1 1 100.00
hmac_test_hmac256_vectors 6.190s 850.969us 1 1 100.00
hmac_test_hmac384_vectors 9.820s 640.913us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 715.796us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.340s 208.181us 1 1 100.00
hmac_long_msg 52.250s 1.195ms 1 1 100.00
hmac_back_pressure 53.850s 1.164ms 1 1 100.00
hmac_datapath_stress 2.684m 6.511ms 1 1 100.00
hmac_burst_wr 23.310s 1.240ms 1 1 100.00
hmac_error 49.380s 3.722ms 1 1 100.00
hmac_wipe_secret 54.060s 5.712ms 1 1 100.00
hmac_test_sha256_vectors 7.660s 191.865us 1 1 100.00
hmac_test_sha384_vectors 18.630s 1.843ms 1 1 100.00
hmac_test_sha512_vectors 18.340s 259.256us 1 1 100.00
hmac_test_hmac256_vectors 6.190s 850.969us 1 1 100.00
hmac_test_hmac384_vectors 9.820s 640.913us 1 1 100.00
hmac_test_hmac512_vectors 10.180s 715.796us 1 1 100.00
hmac_stress_all 5.024m 52.845ms 1 1 100.00
V2 stress_all hmac_stress_all 5.024m 52.845ms 1 1 100.00
V2 alert_test hmac_alert_test 0.620s 15.404us 1 1 100.00
V2 intr_test hmac_intr_test 0.820s 51.124us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.650s 288.805us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.650s 288.805us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.880s 252.089us 1 1 100.00
hmac_csr_rw 0.690s 23.661us 1 1 100.00
hmac_csr_aliasing 5.440s 635.161us 1 1 100.00
hmac_same_csr_outstanding 1.020s 52.594us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.880s 252.089us 1 1 100.00
hmac_csr_rw 0.690s 23.661us 1 1 100.00
hmac_csr_aliasing 5.440s 635.161us 1 1 100.00
hmac_same_csr_outstanding 1.020s 52.594us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.790s 128.582us 1 1 100.00
hmac_tl_intg_err 2.280s 189.508us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.280s 189.508us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.340s 208.181us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.920s 3.369ms 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 34.680s 35.067ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.830s 1.314ms 1 1 100.00
TOTAL 28 28 100.00