I2C Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	59.660s	3.642ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.470s	2.585ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.970s	45.804us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.040s	28.406us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.910s	116.393us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.650s	362.151us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.910s	64.861us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.040s	28.406us	1	1	100.00
		i2c_csr_aliasing	1.650s	362.151us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.750s	107.656us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	1.050m	8.240ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.610s	737.403us	1	1	100.00
V2	host_override	i2c_host_override	0.770s	18.083us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	41.200s	3.037ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.933m	36.086ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.350s	431.726us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.080s	613.572us	1	1	100.00
		i2c_host_fifo_reset_rx	5.880s	279.975us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	43.990s	2.453ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	12.150s	747.270us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.590s	110.400us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.140s	978.641us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	31.010s	33.910ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.390s	2.264ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	18.620s	6.163ms	1	1	100.00
		i2c_target_intr_smoke	3.980s	580.248us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.080s	515.746us	1	1	100.00
		i2c_target_fifo_reset_tx	0.980s	120.396us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.548m	28.462ms	1	1	100.00
		i2c_target_stress_rd	18.620s	6.163ms	1	1	100.00
		i2c_target_intr_stress_wr	11.030s	6.792ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.950s	2.385ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.780s	4.080ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.330s	3.052ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	7.210s	10.635ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.850s	438.709us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.890s	370.939us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.610s	737.403us	1	1	100.00
		i2c_host_perf_precise	1.830s	57.625us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	12.150s	747.270us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.160s	133.368us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.000s	480.913us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.860s	441.879us	1	1	100.00
		i2c_target_nack_txstretch	1.080s	581.890us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.670s	671.095us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.720s	422.031us	1	1	100.00
V2	alert_test	i2c_alert_test	0.780s	15.852us	1	1	100.00
V2	intr_test	i2c_intr_test	0.790s	36.721us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.760s	33.748us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.760s	33.748us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.970s	45.804us	1	1	100.00
		i2c_csr_rw	1.040s	28.406us	1	1	100.00
		i2c_csr_aliasing	1.650s	362.151us	1	1	100.00
		i2c_same_csr_outstanding	1.150s	25.424us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.970s	45.804us	1	1	100.00
		i2c_csr_rw	1.040s	28.406us	1	1	100.00
		i2c_csr_aliasing	1.650s	362.151us	1	1	100.00
		i2c_same_csr_outstanding	1.150s	25.424us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.870s	1.783ms	1	1	100.00
		i2c_sec_cm	1.070s	703.169us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.870s	1.783ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	4.490s	893.914us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.580s	127.886us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	20.340s	1.424ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.88858026649268717081680444911451018534758203902463059296790674048286669087877
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 107656040 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 107656040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.99120542155420181309504560876571790858843925043587915171415182296712352317213
      Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 8239720191 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 8239720191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.38599061115415108084082641728771247183663587713698817453439899634715422782973
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 893913991 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 893913991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.16585626749874580241125382140554473852311893872330212952192883481025986446764
      Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1424443056 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1424443056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.53003666217677035634600351572246139087454127510194896539018421393087728522659
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 978641301 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 978641301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.106916935121670456962189948636942318048840865858188996490743176739789506814091
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 127885832 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 197 [0xc5])
        UVM_INFO @ 127885832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.104222835572003823658539952758486958457256102938876442968133329031935239057584
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10635299749 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10635299749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.83607779791836966507928439219952587749459335337107469546233655031823326973245
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 110400303 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @32330