KEYMGR Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 21.380s 1.500ms 1 1 100.00
V1 random keymgr_random 3.730s 456.431us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.880s 56.825us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.810s 57.233us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.890s 1.334ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 7.690s 1.832ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.160s 20.916us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.810s 57.233us 1 1 100.00
keymgr_csr_aliasing 7.690s 1.832ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 10.390s 267.989us 1 1 100.00
V2 sideload keymgr_sideload 3.410s 167.685us 1 1 100.00
keymgr_sideload_kmac 2.220s 67.709us 1 1 100.00
keymgr_sideload_aes 2.710s 131.646us 1 1 100.00
keymgr_sideload_otbn 2.340s 1.310ms 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.560s 53.143us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.710s 892.568us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.770s 36.839us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 3.410s 103.991us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.010s 123.671us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 3.320s 680.212us 1 1 100.00
V2 stress_all keymgr_stress_all 14.250s 707.697us 1 1 100.00
V2 intr_test keymgr_intr_test 0.740s 43.406us 1 1 100.00
V2 alert_test keymgr_alert_test 0.830s 45.271us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.060s 447.781us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.060s 447.781us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.880s 56.825us 1 1 100.00
keymgr_csr_rw 0.810s 57.233us 1 1 100.00
keymgr_csr_aliasing 7.690s 1.832ms 1 1 100.00
keymgr_same_csr_outstanding 1.180s 104.258us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.880s 56.825us 1 1 100.00
keymgr_csr_rw 0.810s 57.233us 1 1 100.00
keymgr_csr_aliasing 7.690s 1.832ms 1 1 100.00
keymgr_same_csr_outstanding 1.180s 104.258us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
keymgr_tl_intg_err 3.610s 360.434us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 3.500s 1.538ms 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 3.500s 1.538ms 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 3.500s 1.538ms 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 3.500s 1.538ms 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 6.220s 518.380us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 3.610s 360.434us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 3.500s 1.538ms 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 10.390s 267.989us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 3.730s 456.431us 1 1 100.00
keymgr_csr_rw 0.810s 57.233us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 3.730s 456.431us 1 1 100.00
keymgr_csr_rw 0.810s 57.233us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 3.730s 456.431us 1 1 100.00
keymgr_csr_rw 0.810s 57.233us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.710s 892.568us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.010s 123.671us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.010s 123.671us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 3.730s 456.431us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 9.540s 790.077us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.680s 37.167us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.710s 892.568us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.680s 37.167us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.680s 37.167us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.680s 37.167us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 5.310s 3.187ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.680s 37.167us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 14.940s 1.798ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00