| V1 |
smoke |
keymgr_dpe_smoke |
23.230s |
7.728ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.810s |
87.831us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.940s |
15.069us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
7.370s |
459.951us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
3.450s |
237.224us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.100s |
97.539us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.940s |
15.069us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.450s |
237.224us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.110s |
27.424us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.880s |
12.348us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.450s |
81.351us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.450s |
81.351us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.810s |
87.831us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
15.069us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.450s |
237.224us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.390s |
50.673us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.810s |
87.831us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
15.069us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.450s |
237.224us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.390s |
50.673us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.250s |
590.319us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.010s |
100.300us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.580s |
48.377us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.580s |
48.377us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.580s |
48.377us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.580s |
48.377us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
2.740s |
425.809us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.250s |
590.319us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.250s |
590.319us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |