KMAC/MASKED Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	52.730s	7.984ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.770s	66.163us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.970s	28.839us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.010s	4.408ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.380s	2.895ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.770s	186.524us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.970s	28.839us	1	1	100.00
		kmac_csr_aliasing	4.380s	2.895ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.640s	25.772us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.120s	152.235us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	41.634m	247.358ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.545m	3.035ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	1.260s	131.020us	0	1	0.00
		kmac_test_vectors_sha3_256	31.000s	2.071ms	1	1	100.00
		kmac_test_vectors_sha3_384	26.230s	4.266ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.958m	9.697ms	1	1	100.00
		kmac_test_vectors_shake_128	3.217m	17.252ms	1	1	100.00
		kmac_test_vectors_shake_256	1.400m	12.952ms	1	1	100.00
		kmac_test_vectors_kmac	2.100s	540.498us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.790s	86.796us	1	1	100.00
V2	sideload	kmac_sideload	2.441m	12.435ms	1	1	100.00
V2	app	kmac_app	3.955m	6.148ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.395m	5.722ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.970s	874.607us	1	1	100.00
V2	error	kmac_error	1.916m	12.011ms	1	1	100.00
V2	key_error	kmac_key_error	9.500s	11.361ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.810s	1.741ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.600s	322.432us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.390s	98.204us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	56.090s	15.697ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.920s	34.271us	1	1	100.00
V2	stress_all	kmac_stress_all	5.954m	70.671ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.760s	60.105us	1	1	100.00
V2	alert_test	kmac_alert_test	1.180s	80.257us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.770s	271.395us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.770s	271.395us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.770s	66.163us	1	1	100.00
		kmac_csr_rw	0.970s	28.839us	1	1	100.00
		kmac_csr_aliasing	4.380s	2.895ms	1	1	100.00
		kmac_same_csr_outstanding	1.870s	114.771us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.770s	66.163us	1	1	100.00
		kmac_csr_rw	0.970s	28.839us	1	1	100.00
		kmac_csr_aliasing	4.380s	2.895ms	1	1	100.00
		kmac_same_csr_outstanding	1.870s	114.771us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.690s	170.925us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.690s	170.925us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.690s	170.925us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.690s	170.925us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.900s	182.401us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.500m	9.138ms	1	1	100.00
		kmac_tl_intg_err	3.060s	728.584us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.060s	728.584us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.920s	34.271us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	52.730s	7.984ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.441m	12.435ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.690s	170.925us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.500m	9.138ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.500m	9.138ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.500m	9.138ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	52.730s	7.984ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.920s	34.271us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.500m	9.138ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.069m	1.621ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	52.730s	7.984ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	29.230s	5.017ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:

  • Test kmac_test_vectors_sha3_224 has 1 failures.

    • 0.kmac_test_vectors_sha3_224.64586815916527068612959752615193717563359278746670238937992600303885391343265
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest/run.log

        UVM_ERROR @ 131019953 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @ 131019953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.30835819446893533524437528530335536810326602702848789568866127147307316627208
      Line 208, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5016782922 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5016782922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---