MBX Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.150m	3.498ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	1.000s	18.108us	1	1	100.00
V1	csr_rw	mbx_csr_rw	1.000s	20.587us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	4.000s	73.586us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	1.000s	94.779us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	40.928us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	1.000s	20.587us	1	1	100.00
		mbx_csr_aliasing	1.000s	94.779us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	14.000s	10.293ms	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	1.733m	20.323ms	1	1	100.00
V2	mbx_imbx_oob	mbx_imbx_oob	8.000s	88.614us	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	15.000s	11.834ms	1	1	100.00
V2	alert_test	mbx_alert_test	5.000s	52.605us	1	1	100.00
V2	intr_test	mbx_intr_test	3.000s	168.468us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	6.000s	480.488us	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	6.000s	480.488us	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	1.000s	18.108us	1	1	100.00
		mbx_csr_rw	1.000s	20.587us	1	1	100.00
		mbx_csr_aliasing	1.000s	94.779us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	33.597us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	1.000s	18.108us	1	1	100.00
		mbx_csr_rw	1.000s	20.587us	1	1	100.00
		mbx_csr_aliasing	1.000s	94.779us	1	1	100.00
		mbx_same_csr_outstanding	2.000s	33.597us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	mbx_tl_intg_err	5.000s	499.339us	1	1	100.00
		mbx_sec_cm	5.000s	13.949us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			14	16	87.50

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched has 1 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.55182769442879718544896903597290222045322204806226914663914405414379347216604
      Line 235, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 10292959740 ps: (mbx_scoreboard.sv:500) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (1584166739 [0x5e6c7753] vs 0 [0x0]) RDATA read data mismatched
        UVM_INFO @ 10292959740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.63713736220488458439409440309282332397620884364672627264274248289132013240551
      Line 92, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @  88613870 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @  88613870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---