ROM_CTRL/32KB Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.440s 581.159us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.210s 340.541us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.300s 172.715us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.630s 1.161ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.700s 301.134us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.810s 321.197us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.300s 172.715us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 301.134us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.590s 358.843us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.120s 174.730us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.140s 185.201us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.730s 464.972us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.470s 301.158us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.210s 127.191us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.990s 170.250us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.990s 170.250us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.210s 340.541us 1 1 100.00
rom_ctrl_csr_rw 4.300s 172.715us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 301.134us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.470s 795.604us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.210s 340.541us 1 1 100.00
rom_ctrl_csr_rw 4.300s 172.715us 1 1 100.00
rom_ctrl_csr_aliasing 3.700s 301.134us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.470s 795.604us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 17.380s 616.413us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
rom_ctrl_tl_intg_err 25.830s 870.468us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.440s 581.159us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.440s 581.159us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.440s 581.159us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 25.830s 870.468us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.470s 301.158us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 53.890s 9.471ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 17.380s 616.413us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.642m 2.622ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.513m 3.546ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00