0fc384d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.900s | 66.966us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.720s | 15.124us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.730s | 41.064us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.390s | 144.472us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.760s | 116.356us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.870s | 44.780us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.730s | 41.064us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.760s | 116.356us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.700s | 522.631us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 1.980s | 978.017us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 5.675m | 509.279ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 5.675m | 509.279ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 7.090s | 6.838ms | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.630s | 19.053us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.580s | 23.039us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.340s | 78.175us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.340s | 78.175us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.720s | 15.124us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 41.064us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 116.356us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.710s | 19.783us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.720s | 15.124us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.730s | 41.064us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 116.356us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.710s | 19.783us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 1.120s | 129.461us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 0.900s | 187.356us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 0.900s | 187.356us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 1.780s | 1.218ms | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.740s | 60.202us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 11.510s | 1.792ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.92557365448919432513886735051056044497087354072913052467889965244081503448413
Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 1217924813 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5d0ef504) == 0x1
UVM_INFO @ 1217924813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.74630725260636077535267472238738186797536616836192640752263884510234192879015
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 522631319 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfbf3cd04) == 0x1
UVM_INFO @ 522631319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.76742010529100282406417166665558132551610536615218182210905765359296271755687
Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 60201651 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 60201651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---