SPI_DEVICE/1R1W Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	3.119m	154.683ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.260s	58.522us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.910s	219.514us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.680s	1.089ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.420s	2.522ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.890s	218.966us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.910s	219.514us	1	1	100.00
		spi_device_csr_aliasing	17.420s	2.522ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	13.135us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.990s	600.381us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.140s	51.429us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.000s	1.070us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.040s	3.888us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.080s	235.838us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.080s	235.838us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.060s	2.009ms	1	1	100.00
		spi_device_tpm_sts_read	0.930s	89.750us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.470s	10.722ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	15.720s	35.861ms	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	5.800s	3.473ms	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	5.800s	3.473ms	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.450s	224.772us	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.450s	224.772us	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.450s	224.772us	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.450s	224.772us	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.450s	224.772us	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.430s	371.420us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	20.760s	11.815ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	20.760s	11.815ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	20.760s	11.815ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	18.670s	1.912ms	1	1	100.00
		spi_device_read_buffer_direct	6.170s	604.633us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	20.760s	11.815ms	1	1	100.00
		spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.853m	87.200ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.620s	60.561us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.620s	60.561us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	3.119m	154.683ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.876m	18.351ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.171m	45.908ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.890s	12.912us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.040s	13.667us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.020s	68.365us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.020s	68.365us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.260s	58.522us	1	1	100.00
		spi_device_csr_rw	1.910s	219.514us	1	1	100.00
		spi_device_csr_aliasing	17.420s	2.522ms	1	1	100.00
		spi_device_same_csr_outstanding	2.480s	259.892us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.260s	58.522us	1	1	100.00
		spi_device_csr_rw	1.910s	219.514us	1	1	100.00
		spi_device_csr_aliasing	17.420s	2.522ms	1	1	100.00
		spi_device_same_csr_outstanding	2.480s	259.892us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.300s	90.189us	1	1	100.00
		spi_device_tl_intg_err	9.530s	209.789us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.530s	209.789us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.730s	105.870ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.26032489102874704682061344136084292566462563354339676149894130742631015442387
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    882794 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[34])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    882794 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    882794 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[930])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.39099789684699134377582729292980654667621044711218912162932805603304973064727
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1262546 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa0e0cf [101000001110000011001111] vs 0x0 [0])
        UVM_ERROR @   1334546 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2bf971 [1010111111100101110001] vs 0x0 [0])
        UVM_ERROR @   1358546 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8bed2 [10001011111011010010] vs 0x0 [0])
        UVM_ERROR @   1406546 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8cd58b [100011001101010110001011] vs 0x0 [0])
        UVM_ERROR @   1422546 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb22c6f [101100100010110001101111] vs 0x0 [0])