SPI_HOST Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 5.000s 208.102us 1 1 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 2.000s 17.894us 1 1 100.00
V1 csr_rw spi_host_csr_rw 2.000s 62.884us 1 1 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 3.000s 158.761us 1 1 100.00
V1 csr_aliasing spi_host_csr_aliasing 1.000s 30.901us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 2.000s 313.099us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 2.000s 62.884us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.901us 1 1 100.00
V1 mem_walk spi_host_mem_walk 1.000s 42.446us 1 1 100.00
V1 mem_partial_access spi_host_mem_partial_access 2.000s 43.980us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 performance spi_host_performance 1.000s 22.763us 1 1 100.00
V2 error_event_intr spi_host_overflow_underflow 4.000s 312.832us 1 1 100.00
spi_host_error_cmd 2.000s 29.019us 1 1 100.00
spi_host_event 4.000s 733.949us 1 1 100.00
V2 clock_rate spi_host_speed 2.000s 41.403us 1 1 100.00
V2 speed spi_host_speed 2.000s 41.403us 1 1 100.00
V2 chip_select_timing spi_host_speed 2.000s 41.403us 1 1 100.00
V2 sw_reset spi_host_sw_reset 3.000s 90.844us 1 1 100.00
V2 passthrough_mode spi_host_passthrough_mode 2.000s 128.488us 1 1 100.00
V2 cpol_cpha spi_host_speed 2.000s 41.403us 1 1 100.00
V2 full_cycle spi_host_speed 2.000s 41.403us 1 1 100.00
V2 duplex spi_host_smoke 5.000s 208.102us 1 1 100.00
V2 tx_rx_only spi_host_smoke 5.000s 208.102us 1 1 100.00
V2 stress_all spi_host_stress_all 1.617m 11.764ms 1 1 100.00
V2 spien spi_host_spien 5.000s 540.713us 1 1 100.00
V2 stall spi_host_status_stall 24.000s 2.360ms 0 1 0.00
V2 Idlecsbactive spi_host_idlecsbactive 2.000s 97.358us 1 1 100.00
V2 data_fifo_status spi_host_overflow_underflow 4.000s 312.832us 1 1 100.00
V2 alert_test spi_host_alert_test 1.000s 18.185us 1 1 100.00
V2 intr_test spi_host_intr_test 1.000s 173.713us 1 1 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 2.000s 60.689us 1 1 100.00
V2 tl_d_illegal_access spi_host_tl_errors 2.000s 60.689us 1 1 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 2.000s 17.894us 1 1 100.00
spi_host_csr_rw 2.000s 62.884us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.901us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 81.967us 1 1 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 2.000s 17.894us 1 1 100.00
spi_host_csr_rw 2.000s 62.884us 1 1 100.00
spi_host_csr_aliasing 1.000s 30.901us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 81.967us 1 1 100.00
V2 TOTAL 14 15 93.33
V2S tl_intg_err spi_host_tl_intg_err 2.000s 88.491us 1 1 100.00
spi_host_sec_cm 1.000s 178.515us 1 1 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 2.000s 88.491us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_host_upper_range_clkdiv 1.750m 14.152ms 1 1 100.00
TOTAL 25 26 96.15

Failure Buckets