SRAM_CTRL/MAIN Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.250s	2.072ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	84.624us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.020s	122.094us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.490s	721.130us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	124.912us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.250s	1.260ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.020s	122.094us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	124.912us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.058m	37.421ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.867m	5.205ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.780m	76.564ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.582m	5.233ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.234m	632.875ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.497m	51.421ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	50.480s	49.350ms	1	1	100.00
V2	executable	sram_ctrl_executable	41.780s	5.820ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.820s	1.208ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.178m	9.921ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	41.590s	781.334us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.720s	1.750ms	1	1	100.00
		sram_ctrl_throughput_w_readback	21.780s	831.924us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.008m	29.180ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.600s	1.334ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.034h	782.234ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.800s	37.860us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.640s	548.989us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.640s	548.989us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	84.624us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	122.094us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	124.912us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.960s	21.957us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	84.624us	1	1	100.00
		sram_ctrl_csr_rw	1.020s	122.094us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	124.912us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.960s	21.957us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	17.740s	3.864ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
		sram_ctrl_tl_intg_err	1.780s	164.244us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.780s	164.244us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.008m	29.180ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.008m	29.180ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.020s	122.094us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	41.780s	5.820ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	41.780s	5.820ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	41.780s	5.820ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	50.480s	49.350ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.150s	1.393ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	17.740s	3.864ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.560s	792.444us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.250s	2.072ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.250s	2.072ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	41.780s	5.820ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	50.480s	49.350ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.250s	2.072ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.730s	5.260us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.820s	206.329us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.84296757074739995981624899201302268850227666973191475268706657750191745672706
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 792443708 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3d) != exp (0x4b)
        UVM_INFO @ 792443708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.15906103600252574859414291353992215805835649250495087065407899650528887891552
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5259834 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5259834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---