SRAM_CTRL/RET Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.370s	547.078us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.830s	55.043us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.690s	11.266us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.400s	142.632us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.690s	43.094us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.360s	104.958us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.690s	11.266us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	43.094us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.260s	249.030us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.110s	44.908us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	1.275m	6.264ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.153m	7.203ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	50.380s	6.122ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.544m	9.078ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.450s	542.493us	1	1	100.00
V2	executable	sram_ctrl_executable	4.655m	15.948ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	10.930s	299.172us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.433m	30.452ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	27.110s	443.359us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	2.510s	171.793us	1	1	100.00
		sram_ctrl_throughput_w_readback	34.110s	792.855us	1	1	100.00
V2	regwen	sram_ctrl_regwen	29.580s	17.522ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.670s	28.181us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.148m	57.617ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.010s	38.093us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.960s	77.583us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.960s	77.583us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.830s	55.043us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	11.266us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	43.094us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	16.627us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.830s	55.043us	1	1	100.00
		sram_ctrl_csr_rw	0.690s	11.266us	1	1	100.00
		sram_ctrl_csr_aliasing	0.690s	43.094us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	16.627us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.820s	775.859us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
		sram_ctrl_tl_intg_err	1.420s	360.826us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.420s	360.826us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	29.580s	17.522ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	29.580s	17.522ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.690s	11.266us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.655m	15.948ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.655m	15.948ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.655m	15.948ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.450s	542.493us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.970s	39.052us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.820s	775.859us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.060s	87.772us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.370s	547.078us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.370s	547.078us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.655m	15.948ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.450s	542.493us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.370s	547.078us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.730s	2.688us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.690s	195.261us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.71129565774643964872120539861620207156648300891166723822044908144858284594891
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2688386 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2688386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.69801488950302665858591659275616847478447028362931885135250659283878461373541
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 104957843 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (11 [0xb] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @ 104957843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---