UART Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: 0fc384d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.300s	5.383ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.670s	167.390us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.690s	12.319us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.210s	371.188us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	53.072us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.780s	100.380us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.690s	12.319us	1	1	100.00
		uart_csr_aliasing	0.830s	53.072us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	0.760s	429.003us	1	1	100.00
V2	parity	uart_smoke	6.300s	5.383ms	1	1	100.00
		uart_tx_rx	0.760s	429.003us	1	1	100.00
V2	parity_error	uart_intr	25.870s	85.791ms	1	1	100.00
		uart_rx_parity_err	35.400s	27.373ms	1	1	100.00
V2	watermark	uart_tx_rx	0.760s	429.003us	1	1	100.00
		uart_intr	25.870s	85.791ms	1	1	100.00
V2	fifo_full	uart_fifo_full	6.050m	116.600ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	21.130s	144.557ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	28.860s	46.508ms	1	1	100.00
V2	rx_frame_err	uart_intr	25.870s	85.791ms	1	1	100.00
V2	rx_break_err	uart_intr	25.870s	85.791ms	1	1	100.00
V2	rx_timeout	uart_intr	25.870s	85.791ms	1	1	100.00
V2	perf	uart_perf	3.821m	11.885ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.020s	3.357ms	1	1	100.00
V2	line_loopback	uart_loopback	5.020s	3.357ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.010s	4.376ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.520s	3.121ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.340s	6.794ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	41.280s	6.174ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.160m	132.631ms	1	1	100.00
V2	stress_all	uart_stress_all	50.010s	37.471ms	1	1	100.00
V2	alert_test	uart_alert_test	0.810s	48.051us	1	1	100.00
V2	intr_test	uart_intr_test	0.710s	27.066us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	0.910s	39.005us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	0.910s	39.005us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.670s	167.390us	1	1	100.00
		uart_csr_rw	0.690s	12.319us	1	1	100.00
		uart_csr_aliasing	0.830s	53.072us	1	1	100.00
		uart_same_csr_outstanding	0.770s	35.691us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.670s	167.390us	1	1	100.00
		uart_csr_rw	0.690s	12.319us	1	1	100.00
		uart_csr_aliasing	0.830s	53.072us	1	1	100.00
		uart_same_csr_outstanding	0.770s	35.691us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.310s	68.125us	1	1	100.00
		uart_tl_intg_err	1.150s	113.670us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.150s	113.670us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	13.660s	2.538ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.108010950889918116147932254031379764624901441222858540278490210662738934280758
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3048108223 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4,                                 clk_pulses: 0
        UVM_ERROR @ 3048133223 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 3048383223 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 3048408223 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 3048458223 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata