CHIP Simulation Results

Wednesday October 15 2025 16:08:40 UTC

GitHub Revision: `0fc384d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.935m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.935m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.521m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.466m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	49.200s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.121m	4.783ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.121m	4.783ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.121m	4.783ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	31.240s	10.400us	0	1	0.00
		chip_sw_example_manufacturer	2.465m		0	1	0.00
		chip_sw_example_concurrency	4.882m	5.076ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.794s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.920s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.120s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.120s		0	1	0.00
V1	xbar_smoke	xbar_smoke	19.740s	64.657us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.806m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.981m	9.909ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.335m	4.204ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	12.862s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.464s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	38.329s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.242s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.050s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.050s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.108m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.046m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.113m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.113m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.269m	3.702ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.640m	4.691ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.793m	14.299ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.363s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.813s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.435m	13.358ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.069m	4.803ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.543m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.543m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.352s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.103m	4.895ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.103m	4.895ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.129m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.743m	5.335ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.966m	5.782ms	1	1	100.00
		chip_sw_aes_idle	5.167m	5.086ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.395m	4.976ms	1	1	100.00
		chip_sw_kmac_idle	4.083m	3.987ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	14.791m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.746m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.204m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.098m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	16.759s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.415s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.872s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.292s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.275s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.759s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.415s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.872s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.292s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.275s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.361s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.390s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.600s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.050s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.970s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.823s		0	1	0.00
		chip_sw_clkmgr_jitter	3.723m	3.769ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.856m	4.653ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.059s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.920s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.580s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	41.480s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	37.690s	10.100us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.460s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	17.055s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.570s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.416s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.020s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.066m	11.075ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.103m	4.895ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.836s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.066m	11.075ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.100s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	18.842s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	14.988s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.066s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	18.084s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.793m	14.299ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.381m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.097m	8.298ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.095m	10.889ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.359m	3.997ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.920s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.268s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.629s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.095m	10.889ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.414s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.664s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.056s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.986s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.292s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	14.041s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.268s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.255s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.111m	7.153ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.732s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.875s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.958s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.284s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.712m	9.240ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.386m	12.166ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.044s		0	1	0.00
		chip_prim_tl_access	7.356m	8.703ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.759s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.415s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.872s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.292s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.246s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.275s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.275s		0	1	0.00
		chip_rv_dm_lc_disabled	9.435m	13.358ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.665m	4.964ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	38.390s	10.280us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.040m	5.544ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.167m	5.086ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.863m	5.274ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.600s	10.380us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.395m	4.976ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.349m	5.491ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.871m	6.019ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	36.970s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.712m	9.240ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	32.500s	10.380us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.278m	4.554ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.083m	3.987ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.480s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.480s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.994s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.584m	5.096ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.987s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.712m	9.240ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.050s	10.340us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.534s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	16.361s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.966m	5.782ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.966m	5.782ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.966m	5.782ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.462m	5.584ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.386m	12.166ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.386m	12.166ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.464m	9.300ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.823s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.044s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.113m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.462m	5.584ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.712m	9.240ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.464m	9.300ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.315m	4.214ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.462m	5.584ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.712m	9.240ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.464m	9.300ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.315m	4.214ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.619s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	15.255s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.732s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.875s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.958s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.284s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.689s		0	1	0.00
		chip_prim_tl_access	7.356m	8.703ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.356m	8.703ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	16.211s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.150s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.570s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	16.361s		0	1	0.00
		chip_sw_aes_enc_jitter_en	38.390s	10.280us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.600s	10.380us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	41.050s	10.340us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	36.970s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.823s		0	1	0.00
		chip_sw_clkmgr_jitter	3.723m	3.769ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.554m	7.656ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.554m	7.656ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.678m	4.427ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.771m	4.997ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.357m	4.551ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.799m	6.493ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.240m	4.322ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.725m	3.871ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.315m	4.214ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.381m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.381m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.652m	5.516ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.726m	5.588ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.541m	4.300ms	1	1	100.00
		chip_sw_csrng_smoketest	3.272m	3.798ms	1	1	100.00
		chip_sw_gpio_smoketest	3.637m	3.665ms	1	1	100.00
		chip_sw_hmac_smoketest	3.689m	3.741ms	1	1	100.00
		chip_sw_kmac_smoketest	4.285m	5.095ms	1	1	100.00
		chip_sw_otbn_smoketest	5.160m	5.945ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	4.182m	5.815ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.457m	4.043ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.715m	4.279ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.747m	4.265ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.594m	4.490ms	1	1	100.00
		chip_sw_uart_smoketest	4.120m	5.365ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.919s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.794s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.806m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.489s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.771m	5.917ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.383m	4.070ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.078m	5.137ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.073m	4.293ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.910s		0	1	0.00
		chip_rv_dm_lc_disabled	9.435m	13.358ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.114s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.667s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.937s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.686s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.910s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	14.160s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.977s		0	1	0.00
		rom_volatile_raw_unlock	11.909s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.332s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.772m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.706m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.949m	5.066ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.949m	5.066ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.120s		0	1	0.00
		chip_same_csr_outstanding	13.540s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.120s		0	1	0.00
		chip_same_csr_outstanding	13.540s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.087m	171.918us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.500s	12.274us	1	1	100.00
		xbar_smoke_large_delays	3.867m	1.960ms	1	1	100.00
		xbar_smoke_slow_rsp	6.156m	2.190ms	1	1	100.00
		xbar_random_zero_delays	42.440s	37.198us	1	1	100.00
		xbar_random_large_delays	18.253m	9.528ms	1	1	100.00
		xbar_random_slow_rsp	3.862m	1.400ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	16.150s	27.789us	1	1	100.00
		xbar_error_and_unmapped_addr	40.480s	30.294us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.069m	65.129us	1	1	100.00
		xbar_error_and_unmapped_addr	40.480s	30.294us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.421m	69.097us	1	1	100.00
		xbar_access_same_device_slow_rsp	39.635m	15.416ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.021m	369.466us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.298m	244.259us	1	1	100.00
		xbar_stress_all_with_error	17.503m	2.445ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	22.278m	587.335us	1	1	100.00
		xbar_stress_all_with_reset_error	25.561m	3.161ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.026s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.868s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.644s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.453s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.577s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.649s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	12.243s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	14.146s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.073s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.867s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.093s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	25.950s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	58.076s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	54.509s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	58.171s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	48.511s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.606s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	35.036s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	50.346s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	42.400s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	35.447s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	33.160s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	21.583s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	28.150s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	28.610s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.754s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	27.495s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.934s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.601s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	17.233s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.529s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.110s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.299s		0	1	0.00
		rom_e2e_asm_init_dev	12.321s		0	1	0.00
		rom_e2e_asm_init_prod	11.591s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.929s		0	1	0.00
		rom_e2e_asm_init_rma	11.429s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.776s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.913s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.566s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.024s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.448m	5.906ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.388m	5.173ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.583s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.845s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.184s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.890s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	22.180m	16.486ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	16.290s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	19.298m	13.349ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.712s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.101s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.583s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.845s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.184s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.803s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.947s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.922s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.483s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	23.350m	15.140ms	1	1	100.00
		chip_sw_entropy_src_kat_test	3.698m	3.784ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	3.958m	5.500ms	1	1	100.00
		chip_plic_all_irqs_0	8.948m	7.547ms	1	1	100.00
		chip_plic_all_irqs_10	11.675m	7.902ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.520m	5.649ms	1	1	100.00
		chip_sw_dma_abort	4.023m	5.136ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	13.398s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.413s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.709s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.251s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.811s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	13.404s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.902s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.396s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.994s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.860s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.991m	5.232ms	1	1	100.00
		chip_sw_mbx_smoketest	4.960m	6.012ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.14000735607591587356108732464896418657178445781398469741947007144254614516254
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 133.637s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.44397216221727273904994528079478707433066665131568474466627508626789173560485
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.831s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.7918117105308361934390472632192591668321897508568780654117425279486779118627
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.145s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.114123953035356859653042362273480786160481263985094178441118155171134854352853
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 111.176s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.67101190084609033197018208504118832511347076706915954712519994539540966198160
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 104.726s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.44424711432149809838225805196817739640764183897880482976885381457202984645079
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.89262958592119778322507703616702814141086544762307228704459610283588349221886
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.20775055110128292874956347668721349935084150169532126449319119534784629532343
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.109831631874104875648459832785397773189284479959711021608314891103021893560684
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.15462103483843725764433083619506006874208292728253428671410584618688783978695
    Line 385, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.74080989501933893165120478099411769087437279806207679213027817157375936869666
Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12018.387481 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.387481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.78336998340508787663185056390338701857838518182089739631002956962043154658092
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.712195 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.712195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.76933175191784631888530962652127145573415967958999607417977865661486000745733
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.557618 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.557618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.37179868556807610425063687659080119995807278029634863958317459087455303379187
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.814555 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.814555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.18468539825911248347144022026450610583761334858997064960273168910319940735624
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.11503053640245991151576689739083305353553170314901136024432148526845343007556
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.17371018572889281307983712688543778006433240944943134077971381440314966017609
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.115190520496994060136787054521439400959480789851532684342372745739054606271607
    Line 425, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20026.976605 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.976605 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.101895030532136767155217831500571340457586262793874534757472506044775732023703
    Line 397, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18026.874890 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.874890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.
  - 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.87583576836465209974039777210296542058858306918221337362671599116649976832144
    Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log
```
  UVM_ERROR @ 18018.607131 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.607131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.67473582277001110738466498207905495475345837336484034263106287692749090000296
Line 419, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9240.451770 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11947331512723738427166690983712907145968434360516923653830074715172899921040622331081809092533503146603715643962278387364655188952293178449691272422972508 [0xe41d5708aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3624be7f97f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9240.451770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.98189646784952483945590333867132008214573833699767254897277053981496688824449
Line 413, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7152.679450 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (9311069842217351153020111215842989318008720073346844132401425594241646409654375031664771424698772517619695693881231473990986789280035706691277575055301724 [0xb1c78fb4aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd337913f457f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7152.679450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.98163600800321083819080670433541733002423089905843742390474342618212493726972
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3702.241548 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h3c773bda  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h1  a_user: 'h2488e  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3702.241548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.75365688106516176034591710338366897560642359399245944143493203122134195005832
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4690.735713 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h17daf40  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h5  a_opcode: 'h0  a_user: 'h26904  d_param: 'h0  d_source: 'h5  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4690.735713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.26953827669698719033350862920626177747002931869309547127309272047410433740975
    Line 1364, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.88500441148790707349875674731208968726770893657023343439269819035896606378334
    Line 426, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4204.088816 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4204.088816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.41101465359038192130451596946965003281432590914129165648086668390873604756748
    Line 636, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10888.864446 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10888.864446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.69997855604631287995942742139700917246511939899093008144774130070404755976170
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4427.151206 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4427.151206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.89832734370086821720271404051218986555676614044289670055147901086763596963963
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4996.603965 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4996.603965 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.53481985345113874659800033048386149416512126932665784714058313906746920537026
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4894.907675 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4894.907675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.101591427936664910022132112905851881027375664562031487387276928198101248505861
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4322.320384 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4322.320384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.115116778518364402107325181933634623303187800190035068936352549581444493025757
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6492.564576 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6492.564576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.59029058704323780548333582230811363043716939047208342151158741084233986288864
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.99514419072802772947361777344335556086106832156402130127842900558114159611354
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5065.534365 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5065.534365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.101982280385939576156340720243255166671911388694625387584264938400494059156520
    Line 377, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14298.562002 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14298.562002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.113572723578287375050544271768854297285960831024447110061898970377453574575029
    Line 248, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 13357.755788 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x405ec read out mismatch
  UVM_INFO @ 13357.755788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.81945467374320574405173198302179305337144120455272601283028073514140033834625
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.89217235239569683988445534888233484618868747736460978775220183366560835865621
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5135.903136 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5135.903136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```