AES/MASKED Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	102.725us	1	1	100.00
V1	smoke	aes_smoke	2.000s	225.903us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	158.527us	1	1	100.00
V1	csr_rw	aes_csr_rw	1.000s	110.895us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	338.284us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	86.302us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.000s	81.069us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000s	110.895us	1	1	100.00
		aes_csr_aliasing	2.000s	86.302us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	225.903us	1	1	100.00
		aes_config_error	3.000s	655.132us	1	1	100.00
		aes_stress	5.000s	80.166us	1	1	100.00
V2	key_length	aes_smoke	2.000s	225.903us	1	1	100.00
		aes_config_error	3.000s	655.132us	1	1	100.00
		aes_stress	5.000s	80.166us	1	1	100.00
V2	back2back	aes_stress	5.000s	80.166us	1	1	100.00
		aes_b2b	5.000s	191.407us	1	1	100.00
V2	backpressure	aes_stress	5.000s	80.166us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	225.903us	1	1	100.00
		aes_config_error	3.000s	655.132us	1	1	100.00
		aes_stress	5.000s	80.166us	1	1	100.00
		aes_alert_reset	4.000s	284.055us	1	1	100.00
V2	failure_test	aes_man_cfg_err	3.000s	66.151us	1	1	100.00
		aes_config_error	3.000s	655.132us	1	1	100.00
		aes_alert_reset	4.000s	284.055us	1	1	100.00
V2	trigger_clear_test	aes_clear	4.000s	188.934us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	5.950m	32.476ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	284.055us	1	1	100.00
V2	stress	aes_stress	5.000s	80.166us	1	1	100.00
V2	sideload	aes_stress	5.000s	80.166us	1	1	100.00
		aes_sideload	3.000s	76.403us	1	1	100.00
V2	deinitialization	aes_deinit	3.000s	82.751us	1	1	100.00
V2	stress_all	aes_stress_all	20.000s	923.945us	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	90.244us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	78.772us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	78.772us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	158.527us	1	1	100.00
		aes_csr_rw	1.000s	110.895us	1	1	100.00
		aes_csr_aliasing	2.000s	86.302us	1	1	100.00
		aes_same_csr_outstanding	2.000s	205.723us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	158.527us	1	1	100.00
		aes_csr_rw	1.000s	110.895us	1	1	100.00
		aes_csr_aliasing	2.000s	86.302us	1	1	100.00
		aes_same_csr_outstanding	2.000s	205.723us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	7.000s	149.909us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	239.307us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	500.188us	1	1	100.00
		aes_tl_intg_err	2.000s	89.498us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	89.498us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	284.055us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	225.903us	1	1	100.00
		aes_stress	5.000s	80.166us	1	1	100.00
		aes_alert_reset	4.000s	284.055us	1	1	100.00
		aes_core_fi	51.000s	10.017ms	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	152.352us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	112.868us	1	1	100.00
		aes_stress	5.000s	80.166us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	80.166us	1	1	100.00
		aes_sideload	3.000s	76.403us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	112.868us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	112.868us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	112.868us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	112.868us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	112.868us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	80.166us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	80.166us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	184.368us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	184.368us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	65.243us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	184.368us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	284.055us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_ctr_fi	2.000s	53.346us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	184.368us	1	1	100.00
		aes_control_fi	2.000s	61.563us	1	1	100.00
		aes_cipher_fi	2.000s	65.243us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.000s	199.121us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.105116680437950821355934612554822540153474790938793448196449488031135922602286
      Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10016991268 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10016991268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.16664039156995078911984539016411037293802251964971889746236721091837412733618
      Line 162, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 199120893 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @ 199120893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---