CSRNG Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 3.000s 103.307us 1 1 100.00
V1 csr_hw_reset csrng_csr_hw_reset 2.000s 20.406us 1 1 100.00
V1 csr_rw csrng_csr_rw 2.000s 54.371us 1 1 100.00
V1 csr_bit_bash csrng_csr_bit_bash 30.000s 2.931ms 1 1 100.00
V1 csr_aliasing csrng_csr_aliasing 3.000s 158.992us 1 1 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 2.000s 17.535us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 2.000s 54.371us 1 1 100.00
csrng_csr_aliasing 3.000s 158.992us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 interrupts csrng_intr 7.000s 388.606us 1 1 100.00
V2 alerts csrng_alert 9.000s 197.088us 1 1 100.00
V2 err csrng_err 3.000s 110.858us 1 1 100.00
V2 cmds csrng_cmds 1.533m 4.758ms 1 1 100.00
V2 life cycle csrng_cmds 1.533m 4.758ms 1 1 100.00
V2 stress_all csrng_stress_all 1.533m 2.407ms 1 1 100.00
V2 intr_test csrng_intr_test 2.000s 24.553us 1 1 100.00
V2 alert_test csrng_alert_test 2.000s 59.814us 1 1 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 5.000s 89.558us 1 1 100.00
V2 tl_d_illegal_access csrng_tl_errors 5.000s 89.558us 1 1 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 2.000s 20.406us 1 1 100.00
csrng_csr_rw 2.000s 54.371us 1 1 100.00
csrng_csr_aliasing 3.000s 158.992us 1 1 100.00
csrng_same_csr_outstanding 3.000s 82.258us 1 1 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 2.000s 20.406us 1 1 100.00
csrng_csr_rw 2.000s 54.371us 1 1 100.00
csrng_csr_aliasing 3.000s 158.992us 1 1 100.00
csrng_same_csr_outstanding 3.000s 82.258us 1 1 100.00
V2 TOTAL 9 9 100.00
V2S tl_intg_err csrng_sec_cm 3.000s 76.896us 1 1 100.00
csrng_tl_intg_err 9.000s 596.154us 1 1 100.00
V2S sec_cm_config_regwen csrng_regwen 2.000s 33.731us 1 1 100.00
csrng_csr_rw 2.000s 54.371us 1 1 100.00
V2S sec_cm_config_mubi csrng_alert 9.000s 197.088us 1 1 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 1.533m 2.407ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_ctrl_mubi csrng_alert 9.000s 197.088us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 1.533m 2.407ms 1 1 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 9.000s 197.088us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 9.000s 596.154us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
csrng_sec_cm 3.000s 76.896us 1 1 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 7.000s 388.606us 1 1 100.00
csrng_err 3.000s 110.858us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 3.217m 8.863ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00