DMA Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	557.300us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	1.250ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	293.543us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	1.000s	20.555us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	21.497us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	7.188ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	465.116us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	77.274us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	21.497us	1	1	100.00
		dma_csr_aliasing	4.000s	465.116us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	38.000s	17.399ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	7.900m	100.530ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	1.467m	33.956ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	1.467m	33.956ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	7.900m	100.530ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.367m	12.476ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	1.467m	33.956ms	1	1	100.00
V2	dma_abort	dma_abort	5.000s	1.338ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.683m	8.327ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	12.884us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	19.831us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	2.000s	131.877us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	2.000s	131.877us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	1.000s	20.555us	1	1	100.00
		dma_csr_rw	1.000s	21.497us	1	1	100.00
		dma_csr_aliasing	4.000s	465.116us	1	1	100.00
		dma_same_csr_outstanding	2.000s	274.923us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	1.000s	20.555us	1	1	100.00
		dma_csr_rw	1.000s	21.497us	1	1	100.00
		dma_csr_aliasing	4.000s	465.116us	1	1	100.00
		dma_same_csr_outstanding	2.000s	274.923us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	15.000s	136.050us	1	1	100.00
		dma_generic_stress	2.367m	12.476ms	1	1	100.00
		dma_handshake_stress	1.467m	33.956ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	7.000s	339.635us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	1.888ms	1	1	100.00
		dma_sec_cm	1.000s	11.064us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.550m	10.020ms	1	1	100.00
		dma_longer_transfer	4.000s	144.507us	1	1	100.00
		dma_stress_all_with_rand_reset	4.000s	301.755us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.98609668512685750780559061076866081932490426680134818927357868988189421106013
      Line 90, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  301755105ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10008 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  301755105ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---