HMAC Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.750s 1.429ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.700s 46.675us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.900s 17.709us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 6.910s 210.834us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.240s 163.977us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.500s 120.362us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.900s 17.709us 1 1 100.00
hmac_csr_aliasing 2.240s 163.977us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 40.090s 10.560ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.373m 5.491ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.018m 5.334ms 1 1 100.00
hmac_test_sha384_vectors 18.780s 223.357us 1 1 100.00
hmac_test_sha512_vectors 6.540m 47.919ms 1 1 100.00
hmac_test_hmac256_vectors 8.590s 4.366ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 769.939us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 1.577ms 1 1 100.00
V2 burst_wr hmac_burst_wr 14.190s 386.602us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.927m 15.506ms 1 1 100.00
V2 error hmac_error 36.150s 31.699ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 8.850s 1.324ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.750s 1.429ms 1 1 100.00
hmac_long_msg 40.090s 10.560ms 1 1 100.00
hmac_back_pressure 1.373m 5.491ms 1 1 100.00
hmac_datapath_stress 7.927m 15.506ms 1 1 100.00
hmac_burst_wr 14.190s 386.602us 1 1 100.00
hmac_stress_all 18.330s 6.015ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.750s 1.429ms 1 1 100.00
hmac_long_msg 40.090s 10.560ms 1 1 100.00
hmac_back_pressure 1.373m 5.491ms 1 1 100.00
hmac_datapath_stress 7.927m 15.506ms 1 1 100.00
hmac_wipe_secret 8.850s 1.324ms 1 1 100.00
hmac_test_sha256_vectors 3.018m 5.334ms 1 1 100.00
hmac_test_sha384_vectors 18.780s 223.357us 1 1 100.00
hmac_test_sha512_vectors 6.540m 47.919ms 1 1 100.00
hmac_test_hmac256_vectors 8.590s 4.366ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 769.939us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 1.577ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.750s 1.429ms 1 1 100.00
hmac_long_msg 40.090s 10.560ms 1 1 100.00
hmac_back_pressure 1.373m 5.491ms 1 1 100.00
hmac_datapath_stress 7.927m 15.506ms 1 1 100.00
hmac_burst_wr 14.190s 386.602us 1 1 100.00
hmac_error 36.150s 31.699ms 1 1 100.00
hmac_wipe_secret 8.850s 1.324ms 1 1 100.00
hmac_test_sha256_vectors 3.018m 5.334ms 1 1 100.00
hmac_test_sha384_vectors 18.780s 223.357us 1 1 100.00
hmac_test_sha512_vectors 6.540m 47.919ms 1 1 100.00
hmac_test_hmac256_vectors 8.590s 4.366ms 1 1 100.00
hmac_test_hmac384_vectors 7.350s 769.939us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 1.577ms 1 1 100.00
hmac_stress_all 18.330s 6.015ms 1 1 100.00
V2 stress_all hmac_stress_all 18.330s 6.015ms 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 47.638us 1 1 100.00
V2 intr_test hmac_intr_test 0.630s 55.663us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.040s 24.878us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.040s 24.878us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.700s 46.675us 1 1 100.00
hmac_csr_rw 0.900s 17.709us 1 1 100.00
hmac_csr_aliasing 2.240s 163.977us 1 1 100.00
hmac_same_csr_outstanding 1.070s 136.793us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.700s 46.675us 1 1 100.00
hmac_csr_rw 0.900s 17.709us 1 1 100.00
hmac_csr_aliasing 2.240s 163.977us 1 1 100.00
hmac_same_csr_outstanding 1.070s 136.793us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.820s 37.138us 1 1 100.00
hmac_tl_intg_err 2.940s 455.842us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.940s 455.842us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.750s 1.429ms 1 1 100.00
V3 stress_reset hmac_stress_reset 2.690s 294.010us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.569m 1.800ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.840s 66.898us 1 1 100.00
TOTAL 28 28 100.00