I2C Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	23.540s	4.512ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.780s	1.377ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.720s	26.131us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.730s	37.196us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.140s	231.649us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.020s	245.844us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.870s	36.238us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.730s	37.196us	1	1	100.00
		i2c_csr_aliasing	1.020s	245.844us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.350s	194.038us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	11.958m	35.586ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	27.220s	4.837ms	1	1	100.00
V2	host_override	i2c_host_override	0.770s	81.199us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.331m	63.561ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	55.730s	5.303ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.100s	572.569us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.910s	376.749us	1	1	100.00
		i2c_host_fifo_reset_rx	3.470s	157.044us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.259m	12.693ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	13.700s	1.995ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.720s	23.060us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.630s	2.524ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	12.668m	42.115ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.430s	2.731ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.780s	955.809us	1	1	100.00
		i2c_target_intr_smoke	3.630s	3.839ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	0.830s	142.392us	1	1	100.00
		i2c_target_fifo_reset_tx	0.960s	217.508us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.410s	24.517ms	1	1	100.00
		i2c_target_stress_rd	11.780s	955.809us	1	1	100.00
		i2c_target_intr_stress_wr	4.730s	2.511ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.570s	1.233ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.633m	3.018ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.090s	732.629us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.610s	1.310ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.190s	1.889ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.310s	541.294us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	27.220s	4.837ms	1	1	100.00
		i2c_host_perf_precise	6.840s	2.635ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	13.700s	1.995ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.140s	56.272us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.940s	1.009ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.570s	442.858us	1	1	100.00
		i2c_target_nack_txstretch	1.400s	176.493us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	8.020s	283.153us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.690s	474.248us	1	1	100.00
V2	alert_test	i2c_alert_test	0.600s	37.205us	1	1	100.00
V2	intr_test	i2c_intr_test	0.660s	106.490us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.950s	481.187us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.950s	481.187us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.720s	26.131us	1	1	100.00
		i2c_csr_rw	0.730s	37.196us	1	1	100.00
		i2c_csr_aliasing	1.020s	245.844us	1	1	100.00
		i2c_same_csr_outstanding	1.000s	292.553us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.720s	26.131us	1	1	100.00
		i2c_csr_rw	0.730s	37.196us	1	1	100.00
		i2c_csr_aliasing	1.020s	245.844us	1	1	100.00
		i2c_same_csr_outstanding	1.000s	292.553us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	1.220s	240.574us	1	1	100.00
		i2c_sec_cm	0.990s	40.577us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.220s	240.574us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.640s	401.571us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.270s	261.982us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.030s	2.188ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.102633047123624724481809615616812598929754145190943803968813827150874578426412
      Line 151, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 35585688764 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 35585688764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.81852283204283956167711061224757872315622513894572798939039405507472052402380
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  23060227 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  23060227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.75160710031149307276481958473070242922473251420503506714420061767713943682098
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 401571198 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 401571198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.6985380524545438566589710004254228355577616190049165874915046954732407816497
      Line 101, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2188313708 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2188313708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.83076649774107747839459723581603268628308969083191247661421911062917887096057
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 2524294070 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 2524294070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.36511802162806619177147942910944321386661489100643456958507607383611570505281
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 261981826 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 87 [0x57])
        UVM_INFO @ 261981826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---