| V1 |
smoke |
keymgr_dpe_smoke |
11.340s |
1.287ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
0.840s |
24.237us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.880s |
38.177us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
2.960s |
173.470us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
3.290s |
324.170us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
0.850s |
84.400us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.880s |
38.177us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.290s |
324.170us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.790s |
8.154us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.710s |
12.541us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
1.610s |
343.963us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
1.610s |
343.963us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
0.840s |
24.237us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.880s |
38.177us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.290s |
324.170us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.480s |
114.422us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
0.840s |
24.237us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.880s |
38.177us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
3.290s |
324.170us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
1.480s |
114.422us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
8.980s |
1.649ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.180s |
335.209us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
1.380s |
79.420us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
1.380s |
79.420us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
1.380s |
79.420us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
1.380s |
79.420us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
2.040s |
498.474us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
8.980s |
1.649ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
8.980s |
1.649ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |