ROM_CTRL/64KB Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.780s	391.131us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.960s	300.815us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.430s	205.696us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.830s	1.306ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.790s	1.307ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.930s	2.146ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.430s	205.696us	1	1	100.00
		rom_ctrl_csr_aliasing	5.790s	1.307ms	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.940s	299.912us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.480s	302.286us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.820s	315.754us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	21.920s	814.709us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.570s	392.005us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	7.370s	214.280us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.890s	3.123ms	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.890s	3.123ms	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.960s	300.815us	1	1	100.00
		rom_ctrl_csr_rw	6.430s	205.696us	1	1	100.00
		rom_ctrl_csr_aliasing	5.790s	1.307ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.660s	726.798us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.960s	300.815us	1	1	100.00
		rom_ctrl_csr_rw	6.430s	205.696us	1	1	100.00
		rom_ctrl_csr_aliasing	5.790s	1.307ms	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.660s	726.798us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	28.440s	1.756ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
		rom_ctrl_tl_intg_err	1.622m	873.092us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.780s	391.131us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.780s	391.131us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.780s	391.131us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.622m	873.092us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
		rom_ctrl_kmac_err_chk	13.570s	392.005us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.917m	4.500ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	28.440s	1.756ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.835m	2.432ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	23.260s	5.822ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.67446088626206995434741889891059873915759571787442498065483376630470373032241
      Line 245, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 126993651ps failed at 126993651ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 142063914ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 142063914ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))